 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
ID82C52 Datasheet(PDF) 7 Page - Intersil Corporation |
|
||||||||||||||||||||||||||||||
ID82C52 Datasheet(HTML) 7 Page - Intersil Corporation |
|
|
7 / 20 page  7 FN2950.3 April 26, 2006 a buffered version of the data seen on the SDI input and is not a resynchronized output. Also note that normal UART transmission via the Transmitter Register is disabled when operating in the Echo mode (see Figure 4). The Loop Test Mode internally routes transmitted data to the receiver circuitry for the purpose of self test. The transmit data is disabled from the SDO output pin. The Receiver Enable bit gates off the input to the receiver circuitry when in the false state. Modem Interrupt Enable will permit any change in modem status line inputs (CTS, DSR) to cause an interrupt when this bit is enabled. Bit D7 must always be written to with a logic zero to insure correct 82C52 operation. UART Status Register (USR) The USR provides a single register that the controlling sys tem can examine to determine if errors have occurred or if other status changes in the 82C52 require attention. For this reason, the USR is usually the first register read by the CPU to determine the cause of an interrupt or to poll the status of the 82C52. Three error flags OE, FE and PE report the status of any error conditions detected in the receiver circuitry. These error flags are updated with every character received during reception of the stop bits. The Overrun Error (OE) indicates that a character in the Receiver Register has been received and cannot be transferred to the Receiver Buffer Register (RBR) because the RBR was not read by the CPU. Framing Error (FE) indicates that the last character received in the RBR contained improper stop bits. This could be caused by the absence of the required stop bit(s) or by a stop bit(s) that was too short to be properly detected. Parity Error (PE) indicates that the last character received in the RBR contained a parity error based on the programmed parity of the receiver and the calculated parity of the received character data and parity bits. The Received Break (RBRK) status bit indicates that the last character received was a break character. A break character would be considered to be an invalid data character in that the entire character including parity and stop bits are a logic zero. The Modem Status bit is set whenever a transition is detected on any of the Modem input lines (CTS or DSR). A subsequent read of the Modem Status Register will show the state of these two signals. Assertion of this bit will cause an interrupt (INTR) to be generated if the MIEN and INTEN bits in the MCR register are enabled. The Transmission Complete (TC) bit indicates that both the TBR and Transmitter Registers are empty and the 82C52 has completed transmission of the last character it was commanded to transmit. The assertion of this bit will cause an interrupt (INTR) if the INTEN bit in the MCR register is true. The Transmitter Buffer Register Empty (TBRE) bit indicates that the TBR register is empty and ready to receive another character. The Data Ready (DR) bit indicates that the RBR has been loaded with a received character (including Break) and that the CPU may access this data. Assertion of the TBRE or DR bits do not affect the INTR logic and associated INTR output pin since the 82C52 has been designed to provide separate requests via the DR and TBRE output pins. If a single interrupt for any status change in the 82C52 is desired this can be accomplished by using an 82C59A Interrupt controller with DR, TBRE, and INTR as inputs. (See Figure 11). D7 D6 D5 D4 D3 D2 D1 D0 Request to Send (RTS) 0 = RTS Output High † 1 = RTS Output Low Data Terminal Ready (DTR) 0 = DTR Output High 1 = DTR Output Low Interrupt Enable (INTEN) 1 = Interrupts Enabled 0 = interrupts Disabled Mode Select 00 = Normal 01 = Transmit Break 10 = Echo Mode 11 = Loop Test Mode Receiver Enable (REN) 0 = Not Enabled 1 = Enabled Modem Interrupt Enable (MIEN) 0 = Not Enabled 1 = Enabled Must be Set to a Logic 0 for Normal 82C52 Operation † See Modem Status Register description for a description of register flag images with respect to output pins. FIGURE 3. MCR FIGURE 4. LOOP AND ECHO MODE FUNCTIONALITY SERIAL DATA FROM TRANSMITTER REGISTER ECHO MODE SERIAL DATA TO RECEIVER REGISTER SDO PIN 15 SDI PIN 25 LOOP MODE 82C52 82C52 |
Similar Part No. - ID82C52 |
|
Similar Description - ID82C52 |
|
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
