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74HC74N Datasheet(PDF) 8 Page - NXP Semiconductors

Part No. 74HC74N
Description  Dual D-type flip-flop with set and reset; positive edge-trigger
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

74HC74N Datasheet(HTML) 8 Page - NXP Semiconductors

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74HC_HCT74
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 27 August 2012
8 of 21
NXP Semiconductors
74HC74; 74HCT74
Dual D-type flip-flop with set and reset; positive edge-trigger
tsu
set-up time
nD to nCP; see Figure 7
VCC = 2.0 V
75
6
-
90
-
ns
VCC = 4.5 V
15
2
-
18
-
ns
VCC = 6.0 V
13
2
-
15
-
ns
th
hold time
nD to nCP; see Figure 7
VCC = 2.0 V
3
6-
3
-
ns
VCC = 4.5 V
3
2-
3
-
ns
VCC = 6.0 V
3
2-
3
-
ns
fmax
maximum
frequency
nCP; see Figure 7
VCC = 2.0 V
4.8
23
-
4.0
-
MHz
VCC = 4.5 V
24
69
-
20
-
MHz
VCC =5V; CL =15pF
-
76
-
-
-
MHz
VCC = 6.0 V
28
82
-
24
-
MHz
CPD
power
dissipation
capacitance
CL =50pF;f= 1 MHz;
VI =GND to VCC
[4]
-24
-
-
-
pF
74HCT74
tpd
propagation
delay
nCP to nQ, nQ; see
Figure 7
[2]
VCC = 4.5 V
-
18
44
-
53
ns
VCC =5V; CL =15pF
-
15
-
-
-
ns
nSD to nQ, nQ; see
Figure 8
[2]
VCC = 4.5 V
-
23
50
-
60
ns
VCC =5V; CL =15pF
-
18
-
-
-
ns
nRD to nQ, nQ; see
Figure 8
[2]
VCC = 4.5 V
-
24
50
-
60
ns
VCC =5V; CL =15pF
-
18
-
-
-
ns
tt
transition
time
nQ, nQ; see Figure 7
[3]
VCC = 4.5 V
-
7
19
-
22
ns
tW
pulse width
nCP HIGH or LOW;
see Figure 7
VCC = 4.5 V
23
9
-
27
-
ns
nSD, nRD LOW;
see Figure 8
VCC = 4.5 V
20
9
-
24
-
ns
trec
recovery
time
nSD, nRD; see Figure 8
VCC = 4.5 V
8
1
-
9
-
ns
tsu
set-up time
nD to nCP; see Figure 7
VCC = 4.5 V
15
5
-
18
-
ns
Table 8.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 9.
Symbol Parameter
Conditions
Tamb = 40 C to +85 C
Tamb = 40 C to +125 C Unit
Min
Typ[1]
Max
Min
Max


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