ADF4351 datasheet(1/5 Pages) AD

Part #	ADF4351

Description	Increasing the Number of Outputs from a Clock Source Using Low Jitter LVPECL Fanout Buffers

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Circuit Note

CN-0294

Circuits from the Lab™ reference circuits are engineered and

tested for quick and easysystemintegrationto helpsolve today’s

analog, mixed-signal, and RF design challenges. For more

informationand/orsupport,visitwww.analog.com/CN0294.

Devices Connected/Referenced

ADF4351

Fractional-N PLL Synthesizer with

Integrated VCO

ADCLK948

Clock Fanout Buffer with 8 LVPECL

Outputs

Increasing the Number of Outputs from a Clock Source Using Low Jitter LVPECL

Fanout Buffers

Rev. 0

Circuitsfromthe Lab™circuitsfromAnalog Deviceshave been designedandbuiltbyAnalogDevices

engineers. Standard engineering practices have been employed in the design and construction of

eachcircuit,andtheirfunctionandperformancehavebeentestedandverifiedinalabenvironmentat

room temperature. However, you are solely responsible for testing the circuit and determining its

suitabilityandapplicabilityforyouruseandapplication.Accordingly,innoeventshallAnalogDevices

be liable for direct, indirect, special, incidental, consequential or punitive damages due to any cause

whatsoeverconnectedtotheuseofanyCircuitsfromtheLabcircuits. (Continuedonlastpage)

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

Fax: 781.461.3113

EVALUATION AND DESIGN SUPPORT

Circuit Evaluation Boards

ADF4351 Evaluation Board (EVAL-ADF4351EB1Z)

ADCLK948 Evaluation Board (ADCLK948/PCBZ)

Design and Integration Files

Schematics, Layout Files, Bill of Materials

CIRCUIT FUNCTION AND BENEFITS

Many systems require low jitter multiple system clocks for mixed

signal processing and timing. The circuit shown in Figure 1

interfaces the ADF4351 integrated phase-locked loop (PLL)

and voltage-controlled oscillator (VCO) to the ADCLK948,

which provides up to eight differential, low voltage, positive

emitter coupled logic (LVPECL) outputs from one differential

output of the ADF4351.

22nF

10nF

330nF

180

Ω

82

Ω

ADF4351

VVCO

VDD

3.3V

CPGND

AGND

DGND

RFOUTB–

RFOUTB+

CPOUT

1nF

4.7k

Ω

RSET

LE

DATA

CLK

REFIN

FREFIN

VTUNE

DVDD AVDD CE

10

28

16

29

1

2

3

22

8

31

9

11

18

21

27

51

Ω

AGNDVCO

14

15

17

20

7

PDBRF

26

SDGND

6

32

SDVDD

VP

5

SW

4

RFOUTA–

RFOUTA+

13

12

VVCO

ZBIAS

1µF

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

VT0

VREF0

VREF1

IN_SEL

CLK0

VT1

CLK1

LVPECL

ADCLK948

REFERENCE

3.3V

100

Ω

100

Ω

100

Ω 100Ω

1nF

3.3V

Figure 1. ADF4351 PLL Connected to ADCLK948 Fanout Buffer (Simplified Schematic: All Connections and Decoupling Not Shown)

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