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P1AFS1500-QN484I Datasheet(PDF) 25 Page - Microsemi Corporation |
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P1AFS1500-QN484I Datasheet(HTML) 25 Page - Microsemi Corporation |
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25 / 334 page  Fusion Family of Mixed Signal FPGAs Revision 4 2-9 Routing Architecture The routing structure of Fusion devices is designed to provide high performance through a flexible four- level hierarchy of routing resources: ultra-fast local resources; efficient long-line resources; high-speed very-long-line resources; and the high-performance VersaNet networks. The ultra-fast local resources are dedicated lines that allow the output of each VersaTile to connect directly to every input of the eight surrounding VersaTiles (Figure 2-8). The exception to this is that the SET/CLR input of a VersaTile configured as a D-flip-flop is driven only by the VersaNet global network. The efficient long-line resources provide routing for longer distances and higher-fanout connections. These resources vary in length (spanning one, two, or four VersaTiles), run both vertically and horizontally, and cover the entire Fusion device (Figure 2-9 on page 2-10). Each VersaTile can drive signals onto the efficient long-line resources, which can access every input of every VersaTile. Active buffers are inserted automatically by routing software to limit loading effects. The high-speed very-long-line resources, which span the entire device with minimal delay, are used to route very long or high-fanout nets: length ±12 VersaTiles in the vertical direction and length ±16 in the horizontal direction from a given core VersaTile (Figure 2-10 on page 2-11). Very long lines in Fusion devices, like those in ProASIC3 devices, have been enhanced. This provides a significant performance boost for long-reach signals. The high-performance VersaNet global networks are low-skew, high-fanout nets that are accessible from external pins or from internal logic (Figure 2-11 on page 2-12). These nets are typically used to distribute clocks, reset signals, and other high-fanout nets requiring minimum skew. The VersaNet networks are implemented as clock trees, and signals can be introduced at any junction. These can be employed hierarchically, with signals accessing every input on all VersaTiles. Note: Input to the core cell for the D-flip-flop set and reset is only available via the VersaNet global network connection. Figure 2-8 • Ultra-Fast Local Lines Connected to the Eight Nearest Neighbors L L L L L L Inputs Ultra-Fast Local Lines (connects a VersaTile to the adjacent VersaTile, I/O buffer, or memory block) L LL Long Lines |
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