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CN-0279 Datasheet(PDF) 3 Page - Analog Devices |
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CN-0279 Datasheet(HTML) 3 Page - Analog Devices |
3 / 5 page Circuit Note CN-0279 Rev. 0 | Page 3 of 5 Figure 5. Generalized Differential Amplifier/ADC Interface with Band-Pass Filter Filter and Interface Design Procedure In this section, a general approach to the design of the amplifier/ ADC interface with a band-pass filter is presented. To achieve optimum performance (bandwidth, SNR, and SFDR), there are certain design constraints placed on the general circuit by the amplifier and the ADC. 1. The amplifier must see the correct dc load recommended by the data sheet for optimum performance. 2. The correct amount of series resistance must be used between the amplifier and the load presented by the filter. This is to prevent undesired peaking in the pass band. 3. The input to the ADC must be reduced by external parallel resistors, and the correct series resistance must be used to isolate the ADC from the filter. This series resistor also reduces peaking. The generalized circuit shown in Figure 5 applies to most high speed differential amplifier/ADC interfaces and was used as a basis for the band-pass filter. This design approach tends to minimize the insertion loss of the filter by taking advantage of the relatively high input impedance of most high speed ADCs and the relatively low impedance of the driving source (amplifier). The basic design process is as follows: 1. Set the external ADC termination resistors, RTADC, so that the parallel combination of RTADC and RADC is between 200 Ω and 400 Ω. 2. Select RKB based on experience and/or the ADC data sheet recommendations, typically between 5 Ω and 36 Ω. 3. Calculate the filter load impedance using ZAAFL = 2RTADC || (RADC + 2RKB) 4. Select the amplifier external series resistor, RA. Make RA less than 10 Ω if the amplifier differential output impedance is 100 Ω to 200 Ω. Make RA between 5 Ω and 36 Ω if the output impedance of the amplifier is 12 Ω or less. 5. Select ZAAFL so that the total load seen by the amplifier, ZAL, is optimum for the particular differential amplifier chosen using the following equation: ZAL = 2RA + ZAAFL 6. Calculate the filter source resistance by ZAAFS = ZO + 2RA 7. Using a filter design program or tables design the filter using the source and load impedances, ZAAFS and ZAAFL, type of filter, bandwidth, and order. Use a bandwidth that is about 10% higher than the desired bandwidth of the application pass band to ensure flatness in the frequency span. After running these preliminary calculations, the circuit must be given a quick review for the following items. 1. The value of CAAF3 must be at least 10 pF so that it is several times larger than CADC. This minimizes the sensitivity of the filter to variations in CADC. 2. The ratio of ZAAFL to ZAAFS must not be more than about 7 so that the filter is within the limits of most filter tables and design programs. 3. The value of CAAF1 must be at least 5 pF to minimize sensitivity to parasitic capacitance and component variations. 4. The inductor, LAAF, must be a reasonable value of at least several nH. 5. The value of CAFF2 and LAAF1 must be reasonable values. Sometimes circuit simulators can make these values too low or too high. To make these values more reasonable, simply ratio these values with better standard value components that maintain the same resonant frequency. In some cases, the filter design program can provide more than one unique solution, especially with higher order filters. The solution that uses the most reasonable set of component values should always be chosen. Also, choose a configuration that ends in a shunt capacitor so that it can be combined with the ADC input capacitance. 0.1µF 0.1µF 0.1µF CAAF1 CAAF2 CAAF2 LAAF LAAF1 LAAF1 LAAF 0.1µF GAIN CADC XFMR 1:2 Z INPUT Z = 50Ω INTERNAL INPUT Z ADC INTERNAL INPUT Z ZO/2 ZO/2 ZAAFL ZAAFS ZAL AVDD_AMP DRVDD AVDD ANALOG INPUT Z = RI/2 RTADC RTADC 0.1µF RKB RKB RA RI RA RADC CAAF3 VCM |
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