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ADL5565 Datasheet(PDF) 2 Page - Analog Devices |
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ADL5565 Datasheet(HTML) 2 Page - Analog Devices |
2 / 5 page CN-0259 Circuit Note Rev. B | Page 2 of 5 CIRCUIT DESCRIPTION The circuit shown in Figure 1 accepts a single-ended input and converts it to differential using a wide bandwidth (3 GHz) M/A-COM ECT1-1-13M 1:1 transformer. The ADL5565 6.0 GHz differential amplifier has a differential input impedance of 200 Ω when operating at a gain of 6 dB, 100 Ω when operating at a gain of 12 dB, and 67 Ω when operating at a gain of 15.5 dB. The ADL5565 is an ideal driver for the AD6657A, and the fully differential architecture through the low-pass filter and into the ADC provides good high frequency common-mode rejection, as well as minimizes second-order distortion products. The ADL5565 provides a gain of 6 dB, 12 dB, or 15.5 dB depending on the input connection. In the circuit, a gain of 6 dB was used to compensate for the insertion loss of the filter network and the transformer (approximately 2.1 dB), providing an overall signal gain of 4.0 dB. The gain also helps minimize noise impacts from the amplifier. The AD6657A is a quad IF receiver where each ADC output is connected internally to a digital noise shaping requantizer (NSR) block. The integrated NSR circuitry allows for improved SNR performance in a smaller frequency band within the Nyquist bandwidth. The NSR block can be programmed to provide a bandwidth of either 22%, 33%, or 36% of the sampling rate. For the data taken in this circuit note, the sampling rate was 184.32 MSPS, and the following NSR settings applied: • NSR bandwidth = 36% • Tuning word (TW) = 12 • Left band edge = 11.06 MHz (input = 173.26 MHz) • Center frequency = 44.24 MHz (input = 140.08 MHz) • Right band edge = 77.41 MHz (input = 106.91 MHz) Details of the operation of the NSR blocks can be found in the AD6657A data sheet. The antialiasing filter is a fourth-order Butterworth low-pass filter designed with a standard filter design program (Agilent ADS in this case). A Butterworth filter was chosen because of its flat response. A fourth-order filter yields an ac noise bandwidth ratio of 1.03. Other filter design programs are available from Nuhertz Technologies or Quite Universal Circuit Simulator (Qucs) Simulation. To achieve best performance, load the ADL5565 with a net differential load of at least 200 Ω. The 20 Ω series resistors isolate the filter capacitance from the amplifier output and, when added with the downstream impedance, yields a net load impedance of 249 Ω. The 15 Ω resistors in series with the ADC inputs isolate internal switching transients from the filter and the amplifier. The 110 Ω resistors in parallel with the ADC serve to reduce the input impedance of the ADC for more predictable performance. The differential input impedance of the AD6657A is approximately 2.4 kΩ in parallel with 2.2 pF. The real and imaginary components are a function of input frequency for this type of switched capacitor input ADC; the analysis can be found in Application Note AN-742. The fourth-order Butterworth filter was designed with a source impedance of 50 Ω, a load impedance of 209 Ω, and a 3 dB bandwidth of 190 MHz. The final circuit values for the filter are shown in Figure 3. The values generated from the filter program are shown in Figure 2. The values chosen for the filter passive components were the closest standard values to those generated by the program. The internal 2.2 pF capacitance of the ADC was utilized as the final shunt capacitance in the filter design. A small amount of additional shunt capacitance (1.5 pF) was added into the final shunt capacitance at the ADC inputs to help reduce kick back charge currents from the ADC input sampling network and to optimize the filter performance. As seen with this design, obtaining the optimal performance can sometimes be an iterative process. The filter program design values were quite close to the final values, but due to some board parasitics, the final values of the filter were slightly different. Figure 3 shows the final design values for the filter. 110nH 6.0pF 2.2pF 25Ω 209Ω 82nH 110nH 25Ω 82nH Figure 2. Filter Program Initial Design for Fourth-Order Differential Butterworth Filter with ZS = 50 Ω, ZL = 209 Ω, FC = 190 MHz 72nH 7.5pF 3.7pF 25Ω 209Ω 110nH 72nH 25Ω 110nH Figure 3. Final Design Values for Fourth-Order Differential Butterworth Filter with ZS = 50 Ω, ZL = 209 Ω, FC = 190 MHz The measured performance of the system is summarized in Table 1, where the 3 dB bandwidth is 210 MHz. The total insertion loss of the network is approximately 2 dB. The bandwidth response of the final filter circuit is shown in Figure 4, and the SNR, SFDR performance in Figure 5. |
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