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P1AFS1500-QN484 Datasheet(PDF) 86 Page - Microsemi Corporation

Part No. P1AFS1500-QN484
Description  Fusion Family of Mixed Signal FPGAs
Download  334 Pages
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Manufacturer  MICROSEMI [Microsemi Corporation]
Direct Link  http://www.microsemi.com
Logo MICROSEMI - Microsemi Corporation

P1AFS1500-QN484 Datasheet(HTML) 86 Page - Microsemi Corporation

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Device Architecture
2-70
Revision 4
Table 2-32 • RAM512X18
Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
Description
–2
–1
Std.
Units
tAS
Address setup time
0.25 0.28
0.33
ns
tAH
Address hold time
0.00 0.00
0.00
ns
tENS
REN, WEN setup time
0.09 0.10
0.12
ns
tENH
REN, WEN hold time
0.06 0.07
0.08
ns
tDS
Input data (WD) setup time
0.18 0.21
0.25
ns
tDH
Input data (WD) hold time
0.00 0.00
0.00
ns
tCKQ1
Clock High to new data valid on RD (output retained)
2.16 2.46
2.89
ns
tCKQ2
Clock High to new data valid on RD (pipelined)
0.90 1.02
1.20
ns
tC2CRWH1
Address collision clk-to-clk delay for reliable read access after write on
same address—Applicable to Opening Edge
0.50 0.43
0.38
ns
tC2CWRH1
Address collision clk-to-clk delay for reliable write access after read on
same address— Applicable to Opening Edge
0.59 0.50
0.44
ns
tRSTBQ1
RESET Low to data out Low on RD (flow-through)
0.92 1.05
1.23
ns
RESET Low to data out Low on RD (pipelined)
0.92 1.05
1.23
ns
tREMRSTB
RESET removal
0.29 0.33
0.38
ns
tRECRSTB
RESET recovery
1.50 1.71
2.01
ns
tMPWRSTB
RESET minimum pulse width
0.21 0.24
0.29
ns
tCYC
Clock cycle time
3.23 3.68
4.32
ns
FMAX
Maximum frequency
310
272
231
MHz
Notes:
1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-
Based cSoCs and FPGAs.
2. For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9.


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