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P1AFS1500-PQ256 Datasheet(PDF) 42 Page - Microsemi Corporation

Part No. P1AFS1500-PQ256
Description  Fusion Family of Mixed Signal FPGAs
Download  334 Pages
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Manufacturer  MICROSEMI [Microsemi Corporation]
Direct Link  http://www.microsemi.com
Logo MICROSEMI - Microsemi Corporation

P1AFS1500-PQ256 Datasheet(HTML) 42 Page - Microsemi Corporation

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Device Architecture
2-26
Revision 4
Global Buffers with Programmable Delay
The CLKDLY macro is a pass-through clock source that does not use the PLL, but provides the ability to
delay the clock input using a programmable delay (Figure 2-21). The CLKDLY macro takes the selected
clock input and adds a user-defined delay element. This macro generates an output clock phase shift
from the input clock.
The CLKDLY macro can be driven by an INBUF macro to create a composite macro, where the I/O
macro drives the global buffer (with programmable delay) using a hardwired connection. In this case, the
I/O must be placed in one of the dedicated global I/O locations.
Many specific INBUF macros support the wide variety of single-ended and differential I/O standards
supported by the Fusion family. The available INBUF macros are described in the IGLOO, ProASIC3,
SmartFusion and Fusion Macro Library Guide.
The CLKDLY macro can be driven directly from the FPGA core.
The CLKDLY macro can also be driven from an I/O that is routed through the FPGA regular routing
fabric. In this case, users must instantiate a special macro, PLLINT, to differentiate from the hardwired
I/O connection described earlier.
The visual CLKDLY configuration in the SmartGen part of the Libero SoC and Designer tools allows the
user to select the desired amount of delay and configures the delay elements appropriately. SmartGen
also allows the user to select the input clock source. SmartGen will automatically instantiate the special
macro, PLLINT, when needed.
Figure 2-21 • Fusion CCC Options: Global Buffers with Programmable Delay
PADN
PADP
Y
PAD
Y
Input LVDS/LVPECL Macro
INBUF* Macro
GLA
or
GLB
or
GLC
Clock Source
Clock Conditioning
Output
CLK
DLYGL[4:0]
GL


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