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P1AFS600-FG256YI Datasheet(PDF) 85 Page - Microsemi Corporation |
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P1AFS600-FG256YI Datasheet(HTML) 85 Page - Microsemi Corporation |
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85 / 334 page  Fusion Family of Mixed Signal FPGAs Revision 4 2-69 Timing Characteristics Table 2-31 • RAM4K9 Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter Description –2 –1 Std. Units tAS Address setup time 0.25 0.28 0.33 ns tAH Address hold time 0.00 0.00 0.00 ns tENS REN, WEN setup time 0.14 0.16 0.19 ns tENH REN, WEN hold time 0.10 0.11 0.13 ns tBKS BLK setup time 0.23 0.27 0.31 ns tBKH BL hold time 0.02 0.02 0.02 ns tDS Input data (DIN) setup time 0.18 0.21 0.25 ns tDH Input data (DIN) hold time 0.00 0.00 0.00 ns tCKQ1 Clock High to new data valid on DOUT (output retained, WMODE = 0) 1.79 2.03 2.39 ns Clock High to new data valid on DOUT (flow-through, WMODE = 1) 2.36 2.68 3.15 ns tCKQ2 Clock High to new data valid on DOUT (pipelined) 0.89 1.02 1.20 ns tC2CWWH1 Address collision clk-to-clk delay for reliable write after write on same address—Applicable to Rising Edge 0.30 0.26 0.23 ns tC2CRWH1 Address collision clk-to-clk delay for reliable read access after write on same address—Applicable to Opening Edge 0.45 0.38 0.34 ns tC2CWRH1 Address collision clk-to-clk delay for reliable write access after read on same address— Applicable to Opening Edge 0.49 0.42 0.37 ns tRSTBQ RESET Low to data out Low on DOUT (flow-through) 0.92 1.05 1.23 ns RESET Low to Data Out Low on DOUT (pipelined) 0.92 1.05 1.23 ns tREMRSTB RESET removal 0.29 0.33 0.38 ns tRECRSTB RESET recovery 1.50 1.71 2.01 ns tMPWRSTB RESET minimum pulse width 0.21 0.24 0.29 ns tCYC Clock cycle time 3.23 3.68 4.32 ns FMAX Maximum frequency 310 272 231 MHz Notes: 1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for Flash- Based cSoCs and FPGAs. 2. For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9. |
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