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P1AFS600-QN256YI Datasheet(PDF) 63 Page - Microsemi Corporation |
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P1AFS600-QN256YI Datasheet(HTML) 63 Page - Microsemi Corporation |
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63 / 334 page  Fusion Family of Mixed Signal FPGAs Revision 4 2-47 Access to the FB is controlled by the BUSY signal. The BUSY output is synchronous to the CLK signal. FB operations are only accepted in cycles where BUSY is logic 0. Write Operation Write operations are initiated with the assertion of the WEN signal. Figure 2-35 on page 2-47 illustrates the multiple Write operations. When a Write operation is initiated to a page that is currently not in the Page Buffer, the FB control logic will issue a BUSY signal to the user interface while the page is loaded from the FB Array into the Page Buffer. A Copy Page operation takes no less than 55 cycles and could take more if a Write or Unprotect Page operation is started while the NVM is busy pre-fetching a block. The basic operation is to read a block from the array into the block register (5 cycles) and then write the block register to the page buffer (1 cycle) and if necessary, when the copy is complete, reading the block being written from the page buffer into the block buffer (1 cycle). A page contains 9 blocks, so 9 blocks multiplied by 6 cycles to read/write each block, plus 1 is 55 cycles total. Subsequent writes to the same block of the page will incur no busy cycles. A write to another block in the page will assert BUSY for four cycles (five cycles when PIPE is asserted), to allow the data to be written to the Page Buffer and have the current block loaded into the Block Buffer. Write operations are considered successful as long as the STATUS output is '00'. A non-zero STATUS indicates that an error was detected during the operation and the write was not performed. Note that the STATUS output is "sticky"; it is unchanged until another operation is started. Only one word can be written at a time. Write word width is controlled by the DATAWIDTH bus. Users are responsible for keeping track of the contents of the Page Buffer and when to program it to the array. Just like a regular RAM, writing to random addresses is possible. Users can write into the Page Buffer in any order but will incur additional BUSY cycles. It is not necessary to modify the entire Page Buffer before saving it to nonvolatile memory. Write errors include the following: 1. Attempting to write a page that is Overwrite Protected (STATUS = '01'). The write is not performed. 2. Attempting to write to a page that is not in the Page Buffer when Page Loss Protection is enabled (STATUS = '11'). The write is not performed. Figure 2-35 • FB Write Waveform CLK WEN ADDR[17:0] WD[31:0] DATAWIDTH[1:0] PAGELOSSPROTECT BUSY STATUS[1:0] A0 A1 A2 A3 A4 A5 A6 D0 D1 D2 D3 D4 D5 D6 S0 S1 S2 S3 S4 S5 S6 |
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