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P1AFS600-PQ484 Datasheet(PDF) 70 Page - Microsemi Corporation

Part No. P1AFS600-PQ484
Description  Fusion Family of Mixed Signal FPGAs
Download  334 Pages
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Manufacturer  MICROSEMI [Microsemi Corporation]
Direct Link  http://www.microsemi.com
Logo MICROSEMI - Microsemi Corporation

P1AFS600-PQ484 Datasheet(HTML) 70 Page - Microsemi Corporation

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Device Architecture
2-54
Revision 4
Flash Memory Block Characteristics
Figure 2-44 • Reset Timing Diagram
Table 2-25 • Flash Memory Block Timing
Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
Description
–2
–1
Std.
Units
tCLK2RD
Clock-to-Q in 5-cycle read mode of the Read Data
7.99
9.10
10.70
ns
Clock-to-Q in 6-cycle read mode of the Read Data
5.03
5.73
6.74
ns
tCLK2BUSY
Clock-to-Q in 5-cycle read mode of BUSY
4.95
5.63
6.62
ns
Clock-to-Q in 6-cycle read mode of BUSY
4.45
5.07
5.96
ns
tCLK2STATUS
Clock-to-Status in 5-cycle read mode
11.24
12.81
15.06
ns
Clock-to-Status in 6-cycle read mode
4.48
5.10
6.00
ns
tDSUNVM
Data Input Setup time for the Control Logic
1.92
2.19
2.57
ns
tDHNVM
Data Input Hold time for the Control Logic
0.00
0.00
0.00
ns
tASUNVM
Address Input Setup time for the Control Logic
2.76
3.14
3.69
ns
tAHNVM
Address Input Hold time for the Control Logic
0.00
0.00
0.00
ns
tSUDWNVM
Data Width Setup time for the Control Logic
1.85
2.11
2.48
ns
tHDDWNVM
Data Width Hold time for the Control Logic
0.00
0.00
0.00
ns
tSURENNVM
Read Enable Setup time for the Control Logic
3.85
4.39
5.16
ns
tHDRENNVM
Read Enable Hold Time for the Control Logic
0.00
0.00
0.00
ns
tSUWENNVM
Write Enable Setup time for the Control Logic
2.37
2.69
3.17
ns
tHDWENNVM
Write Enable Hold Time for the Control Logic
0.00
0.00
0.00
ns
tSUPROGNVM
Program Setup time for the Control Logic
2.16
2.46
2.89
ns
tHDPROGNVM
Program Hold time for the Control Logic
0.00
0.00
0.00
ns
tSUSPAREPAGE
SparePage Setup time for the Control Logic
3.74
4.26
5.01
ns
tHDSPAREPAGE
SparePage Hold time for the Control Logic
0.00
0.00
0.00
ns
tSUAUXBLK
Auxiliary Block Setup Time for the Control Logic
3.74
4.26
5.00
ns
tHDAUXBLK
Auxiliary Block Hold Time for the Control Logic
0.00
0.00
0.00
ns
tSURDNEXT
ReadNext Setup Time for the Control Logic
2.17
2.47
2.90
ns
tHDRDNEXT
ReadNext Hold Time for the Control Logic
0.00
0.00
0.00
ns
tSUERASEPG
Erase Page Setup Time for the Control Logic
3.76
4.28
5.03
ns
tHDERASEPG
Erase Page Hold Time for the Control Logic
0.00
0.00
0.00
ns
tSUUNPROTECTPG
Unprotect Page Setup Time for the Control Logic
2.01
2.29
2.69
ns
tHDUNPROTECTPG
Unprotect Page Hold Time for the Control Logic
0.00
0.00
0.00
ns
tSUDISCARDPG
Discard Page Setup Time for the Control Logic
1.88
2.14
2.52
ns
tHDDISCARDPG
Discard Page Hold Time for the Control Logic
0.00
0.00
0.00
ns
tSUOVERWRPRO
Overwrite Protect Setup Time for the Control Logic
1.64
1.86
2.19
ns
tHDOVERWRPRO
Overwrite Protect Hold Time for the Control Logic
0.00
0.00
0.00
ns
CLK
RESET
Active Low, Asynchronous
BUSY


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