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P1AFS600-1FG256 Datasheet(PDF) 48 Page - Microsemi Corporation

Part No. P1AFS600-1FG256
Description  Fusion Family of Mixed Signal FPGAs
Download  334 Pages
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Manufacturer  MICROSEMI [Microsemi Corporation]
Direct Link  http://www.microsemi.com
Logo MICROSEMI - Microsemi Corporation

P1AFS600-1FG256 Datasheet(HTML) 48 Page - Microsemi Corporation

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Device Architecture
2-32
Revision 4
The NGMUX macro is simplified to show the two clock options that have been selected by the
GLMUXCFG[1:0] bits. Figure 2-25 illustrates the NGMUX macro. During design, the two clock sources
are connected to CLK0 and CLK1 and are controlled by GLMUXSEL[1:0] to determine which signal is to
be passed through the MUX.
The sequence of switching between two clock sources (from CLK0 to CLK1) is as follows (Figure 2-26):
GLMUXSEL[1:0] transitions to initiate a switch.
GL drives one last complete CLK0 positive pulse (i.e., one rising edge followed by one falling
edge).
From that point, GL stays Low until the second rising edge of CLK1 occurs.
At the second CLK1 rising edge, GL will begin to continuously deliver the CLK1 signal.
Minimum tsw = 0.05 ns at 25°C (typical conditions)
For examples of NGMUX operation, refer to the Fusion FPGA Fabric User’s Guide.
Figure 2-25 • NGMUX Macro
Figure 2-26 • NGMUX Waveform
CLK0
CLK1
GL
GLMUXSEL[1:0]
CLK0
CLK1
GLMUXSEL[1:0]
GL
tSW


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