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RS2253 Datasheet(PDF) 6 Page - Orister Corporation |
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RS2253 Datasheet(HTML) 6 Page - Orister Corporation |
6 / 9 page Page No. : 6/9 DS‐RS2253‐11 May, 2010 www.Orister.com Internal synchronized Slope Compensation Built‐in slope compensation circuit adds voltage ramp onto the current sense input voltage for PWM generation. This greatly improves the close loop stability at CCM and prevents the sub‐harmonic oscillation and thus reduces the output ripple voltage. Drive The internal power MOSFET in RS2253 is driven by a dedicated gate driver for power switch control. Too weak the gate driving strength results in higher conduction and switch loss of MOSFET while too strong gate drive results the compromise of EMI. A good tradeoff is achieved through the built‐in totem pole gate design with right output strength and dead time control. The low idle loss and good EMI system design is easier to achieve with this dedicated control scheme. In addition to the gate drive control scheme mentioned, the gate drive strength can also be adjusted externally by a resistor connected between VDD and VDDG, the falling edge of the Drain output can be well controlled. It provides great flexibility for system EMI design. Protection Controls Good power supply system reliability is achieved with its rich protection features including Cycle‐by‐Cycle current limiting (OCP), Over Load Protection (OLP) and over voltage clamp, Under Voltage Lockout on VDD (UVLO). With Orister Proprietary technology, the OCP is line voltage compensated to achieve constant output power limit over the universal input voltage range. At overload condition when FB input voltage exceeds power limit threshold value for more than TD_PL, control circuit reacts to shut down the switcher. Switcher restarts when VDD voltage drops below UVLO limit. VDD is supplied by transformer auxiliary winding output. It is clamped when VDD is higher than 30V. The output of RS2253 is shut down when VDD drops below UVLO(ON) limit and Switcher enters power on start‐up sequence thereafter. |
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