LTC2912

6

2912fa

BLOCK DIAGRAM

0.5V

3

VL

2

VH

+

–

UVLO

UVLO

2V

+

–

1V

OV PULSE

GENERATOR

DISABLE

DISABLE

OV LATCH

CLEAR/BYPASS

LTC2912-1, LTC2912-3

TMR

4

OV/OV

6

LATCH

8

1V

2μA

DIS

8

GND

2912 BD

5

1

UV PULSE

GENERATOR

OSCILLATOR

400k

UV

7

400k

LTC2912-1

LTC2912-2

LTC2912-3

LTC2912-2

OV (Pin 6/Pin 3, LTC2912-3): Overvoltage Logic Output.

VL input is above threshold. Latches high. May be pulled

unused.

TMR (Pin 4/Pin 5): Reset Delay Timer. Attach an external

delay time of 9ms/nF. A 1nF capacitor will generate an

UV (Pin 7/Pin 2): Undervoltage Logic Output. Asserts low

when the VH input voltage is below threshold. Held low for

a programmed delay time after the VH input is valid. Pin

using an external pull-up. Leave pin open if unused.

GND with a 0.1μF (or greater) capacitor. Operates as a

direct supply input for voltages up to 6V. Operates as a

shunt regulator for supply voltages greater than 6V and

should have a resistance between the pin and the supply

to limit input current to no greater than 10mA. When used

without a current-limiting resistance, pin voltage must

not exceed 6V.

VH (Pin 2/Pin 7): Voltage High Input. When the voltage

on this pin is below 0.5V, an undervoltage condition is

VL (Pin 3/Pin 6): Voltage Low Input. When the voltage on

this pin is above 0.5V, an overvoltage condition is triggered.

Tie pin to GND if unused.