THS1031

3-V TO 5.5-V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002

6

POST OFFICE BOX 655303

dc accuracy

PARAMETER

MIN

TYP

MAX

UNIT

INL

Integral nonlinearity (see Note 1)

±1

±2

LSB

DNL

Differential nonlinearity (see Note 2)

±0.3

±1

LSB

Offset error (see Note 3)

0.4

2

%FSR

Gain error (see Note 4)

1.4

3.5

%FSR

Missing code

No missing code assured

NOTES:

1. Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero to full scale. The point used as zero

occurs 1/2 LSB before the first code transition. The full-scale point is defined as a level 1/2 LSB beyond the last code transition. The

deviation is measured from the center of each particular code to the true straight line between these two endpoints.

2. An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Therefore this measure

indicates how uniform the transfer function step sizes are. The ideal step size is defined here as the step size for the device under

test (i.e., (last transition level – first transition level)

÷ (2 n – 2)). Using this definition for DNL separates the effects of gain and offset

error. A minimum DNL better than –1 LSB ensures no missing codes.

3. Offset error is defined as the difference in analog input voltage – between the ideal voltage and the actual voltage – that will switch

the ADC output from code 0 to code 1. The ideal voltage level is determined by adding the voltage corresponding to 1/2 LSB to the

bottom reference level. The voltage corresponding to 1 LSB is found from the difference of top and bottom references divided by

the number of ADC output levels (1024).

4. Gain error is defined as the difference in analog input voltage – between the ideal voltage and the actual voltage – that will switch

the ADC output from code 1022 to code 1023. The ideal voltage level is determined by subtracting the voltage corresponding to 1.5

LSB from the top reference level. The voltage corresponding to 1 LSB is found from the difference of top and bottom references

divided by the number of ADC output levels (1024).

dynamic performance (ADC and PGA)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

f = 3.5 MHz

8.2

9

ENOB

Effective number of bits

f = 3.5 MHz, AVDD = 5 V

8.8

Bits

ENOB

Effective number of bits

f = 15 MHz

7.7

Bits

f = 15 MHz, AVDD = 5 V

7.64

f = 3.5 MHz

55

60

SFDR

Spurious free dynamic range

f = 3.5 MHz, AVDD = 5 V

63

dB

SFDR

Spurious free dynamic range

f = 15 MHz

48

dB

f = 15 MHz, AVDD = 5 V

52.4

f = 3.5 MHz

– 58.2

– 54.7

THD

Total harmonic distortion

f = 3.5 MHz, AVDD = 5 V

– 68.7

dB

THD

Total harmonic distortion

f = 15 MHz

– 47

dB

f = 15 MHz, AVDD = 5 V

– 51.9

f = 3.5 MHz

51.2

56

SNR

Signal to noise ratio

f = 3.5 MHz, AVDD = 5 V

55

dB

SNR

Signal-to-noise ratio

f = 15 MHz

53

dB

f = 15 MHz, AVDD = 5 V

49.3

f = 3.5 MHz

51.1

56

SINAD

Signal to noise and distortion

f = 3.5 MHz, AVDD = 5 V

55

dB

SINAD

Signal-to-noise and distortion

f = 15 MHz

48.1

dB

f = 15 MHz, AVDD = 5 V

47.7