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5AGTFD3G427C4N Datasheet(PDF) 7 Page - Altera Corporation |
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5AGTFD3G427C4N Datasheet(HTML) 7 Page - Altera Corporation |
7 / 82 page AV51001-1.3 © 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. Arria V Device Handbook Volume 1: Device Overview and Datasheet February 2012 Subscribe ISO 9001:2008 Registered 1. Overview for the Arria V Device Family Built on the 28-nm low-power process technology, Arria® V devices offer the lowest power and lowest system cost for mainstream applications. Arria V devices include unique innovations such as the lowest static power in its class, the lowest power transceivers of any midrange family, support for serial data rates up to 10.3125 gigabits per second (Gbps), a powerful collection of integrated hard intellectual property (IP), and a power-optimized core architecture, making Arria V devices ideal for the following applications: ■ Power sensitive wireless infrastructure equipment ■ 20G/40G bridging, switching, and packet processing applications ■ High-definition video processing and image manipulation ■ Intensive digital signal processing (DSP) applications Arria V devices are available in the following variants: ■ Arria V GX—FPGA with integrated 6-Gbps transceivers, this variant provides bandwidth, cost, and power levels that are optimized for high-volume data and signal-processing applications. ■ Arria V GT—FPGA with integrated 10-Gbps transceivers, this variant provides enhanced high-speed serial I/O bandwidth for cost-sensitive data and signal processing applications. ■ Arria V SX—system-on-a-chip (SoC) FPGA with integrated Arria V FPGA and ARM®-based hard processor system (HPS). ■ Arria V ST—SoC FPGA with integrated Arria V FPGA, ARM-based HPS, and 10-Gbps transceivers. The Arria V SoC FPGA variants feature an FPGA integrated with an HPS that consists of a dual-core ARM Cortex™-A9 MPCore™ processor, a rich set of peripherals, and a shared multiport SDRAM memory controller. The unique feature set in Arria V devices was chosen to optimize power, cost, and performance. These features include a redesigned adaptive logic module (ALM), distributed memory, new 10-Kbit (M10K) internal memory blocks, variable-precision DSP blocks, and fractional clock synthesis phase-locked loops (PLLs) with a highly flexible clocking network, all interconnected by a power-optimized MultiTrack routing architecture. February 2012 AV51001-1.3 |
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