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744309025 Datasheet(PDF) 4 Page - International Rectifier |
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744309025 Datasheet(HTML) 4 Page - International Rectifier |
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4 / 53 page  IR3846 4 www.irf.com © 2013 International Rectifier August 01, 2013 PIN DESCRIPTIONS PIN # PIN NAME PIN DESCRIPTION 1 PVin Input voltage for power stage. Bypass capacitors between PVin and PGND should be connected very close to this pin and PGND; also forms input to feedforward block 2, 3, 22, 23, 26 NC No Connect 4 Boot Supply voltage for high side driver 5 Enable Enable pin to turning on and off the IC. 6 Rt/Sync Use an external resistor from this pin to LGND to set the switching frequency, very close to the pin. This pin can also be used for external synchronization. 7 OCset Current limit setpoint. This pin allows the trip point to be set to one of three possible settings by either floating this pin, tying it to VCC or tying it to PGnd. 8 Vsns Sense pin for OVP and PGood 9 FB Inverting input to the error amplifier. This pin is connected directly to the output of the regulator or to the output of the remote sense amplifier, via resistor divider to set the output voltage and provide feedback to the error amplifier. 10 COMP Output of error amplifier. An external resistor and capacitor network is typically connected from this pin to FB to provide loop compensation. 11 RSo Remote Sense Amplifier Output 12, 25 PGND Power ground. This pin should be connected to the system’s power ground plane. Bypass capacitors between PVin and PGND should be connected very close to PVIN pin (pin 1) and this pin. 13 LGND Signal ground for internal reference and control circuitry. 14 S_Ctrl Soft start/stop control. A high logic input enables the device to go into the internal soft start; a low logic input enables the output soft discharged. Pull this pin high if this function is not used. 15 RS- Remote Sense Amplifier input. Connect to ground at the load. 16 RS+ Remote Sense Amplifier input. Connect to output at the load. 17 Vref External reference voltage can be used for margining operation. A capacitor between 100pF and 180pF should be connected between this pin and LGnd. Tie to LGnd for tracking function. 18 Vp Used for voltage sequencing and tracking. Leave open if sequencing or tracking is not needed, ensuring that there is no capacitor on the pin. 19 PGD Power Good status pin. Output is open drain. Connect a pull up resistor from this pin to VCC. 20 Vin Input Voltage for LDO. 21 VCC/LDO_out Bias Voltage for IC and driver section, output of LDO. Add a minimum of 4.7uF bypass cap from this pin to PGnd. 24 SW Switch node. This pin is connected to the output inductor. |
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