Package Plan

Table 7: Package Plan for Arria V GT Devices—Preliminary

F1517

(40 mm)

F1152

(35 mm)

F896

(31 mm)

F672

(27 mm)

Mem-

ber

Code

XCVR

GPIO

XCVR

GPIO

XCVR

GPIO

XCVR

GPIO

10-

Gbps

6-Gbps

10-

Gbps

6-Gbps

10-

Gbps

6-Gbps

10-

Gbps

6-Gbps

—

—

—

—

—

—

4

3 (9)

416

4

3 (9)

336

C3

—

—

—

12

6 (24)

544

8

6 (18)

384

—

—

—

C7

12

6 (24)

704

12

6 (24)

544

8

6 (18)

384

—

—

—

D3

20

6 (36)

704

12

6 (24)

544

—

—

—

—

—

—

D7

The 6-Gbps transceiver counts are for dedicated 6-Gbps channels. You can also configure any pair of 10-Gbps

channels as three 6-Gbps channels—the total number of 6-Gbps channels are shown in brackets. For example,

you can also configure the Arria V GT D7 device in the F1517 package with nine 6-Gbps and eighteen

10-Gbps, twelve 6-Gbps and sixteen 10-Gbps, fifteen 6-Gbps and fourteen 10-Gbps, or up to thirty-six

6-Gbps with no 10-Gbps channels.

Arria V GZ

This section provides the available options, maximum resource counts, and package plan for the Arria V GZ

devices.

Available Options

Figure 3: Sample Ordering Code and Available Options for Arria V GZ Devices—Preliminary

Family Signature

Embedded Hard IPs

Transceiver Count

Maximum channels

Transceiver

Speed Grade

Package Type

Package Code

Operating Temperature

FPGA Fabric

Speed Grade

Optional Suffix

Indicates specific device

options or shipment method

GZ : 12.5-Gbps transceivers

M : 1 hard PCIe controller

5A : Arria V

E1 : 220K logic elements

E3 : 360K logic elements

E5 : 400K logic elements

E7 : 450K logic elements

E : 12

H : 24

K : 36

2 : 12.5 Gbps

3 : 10.3125 Gbps

F : FineLine BGA (FBGA)

H : Hybrid FBGA

29 : 780 pins

35 : 1,152 pins

40 : 1,517 pins

3 (fastest)

4

N : Lead-free packaging

L : Low-power device

5A

GZ

M

E7

K

2

F

40

C

3

N

Member Code

Family Variant

I

Note: Low-power device option is available only for –3 speed grade at industrial temperature

Altera Corporation

Arria V Device Overview

Feedback

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Package Plan

AV-51001

2013.05.06