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HI-8685PSTF-10 Datasheet(PDF) 3 Page - Holt Integrated Circuits |
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HI-8685PSTF-10 Datasheet(HTML) 3 Page - Holt Integrated Circuits |
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3 / 12 page  HI-8685, HI-8686 PROTOCOL DETECTION The ARINC clock and One/Zero data that are derived from the outputs of the built-in line receiver is illustrated in Figure 3. The resulting steam of digital data is shifted into a 32-bit input register. The ARINC clock and One/Zero data can also be created from the TESTA and TESTB inputs as shown in Figure 4. When either test input is high, the built-in analog line driver is disabled. digital For ARINC 561 operation, the TESTA and TESTB digital in- put data streams must be derived from the ARINC 561 data, clock and sync with external logic. GAP DETECTION The end of a data word is detected by an internal counter that times out when a data One or Zero is not received for a period equal to 16 cycles of the GAPCLK signal. The gap detection time may vary between 16 and 17 cycles of the GAPCLK signal since the incoming data and GAPCLK are not usually synchronous inputs. The required frequency of GAPCLK is a function of the mininum gap time specified for the type of ARINC data being received. Table 1 indicates typical frequencies that may be used for the various data rates normally encountered. BIT COUNT PARITY DETECT GAP DETECT 32-BIT SHIFT REG. 32-BIT RECEIVE BUFFER 32-BIT TO 16-BIT MUX ERROR DETECT CLOCK & DATA DETECT PARITY ENB RINB TESTA TESTB GAPCLK RESET BYTE COUNT READ DATA RDY ERROR 32 16 32 Figure 1. Block Diagram ESD PROTECTION & LINE RECEIVER DATABUS BIT PERIOD MINIMUM GAP GAP CLOCK GAP DETECTION TYPE (µs) (µs) MHz TIME (µs) 429 10 45 0.75 21.3 - 22.7 1.0 16 - 17 1.5 10.7 - 11.3 429 69 - 133 310 - 599 0.1 160 - 170 575 69 - 133 310 - 599 0.1 160 - 170 561 69 - 133 103 - 200 0.2 80 - 85 Table1-Typical Gap Detection Times FUNCTIONAL DESCRIPTION (cont.) RXA RXB 10K W BIT 32 BIT 32 RINA 10K W D0 - D15 25K W 25K W RINB-10 RINA-10 DATA CLK HOLT INTEGRATED CIRCUITS 3 |
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