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EP1C6Q400C6ES Datasheet(PDF) 5 Page - Altera Corporation |
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EP1C6Q400C6ES Datasheet(HTML) 5 Page - Altera Corporation |
5 / 106 page Altera Corporation 1–3 May 2008 Preliminary Document Revision History to the appropriate plane on the board. The Quartus II software reserves I/O pins as power pins as necessary for layout with the larger densities in the same package having more power pins. Document Revision History Table 1–4 shows the revision history for this document. Table 1–3. Cyclone QFP and FineLine BGA Package Sizes Dimension 100-Pin TQFP 144-Pin TQFP 240-Pin PQFP 256-Pin FineLine BGA 324-Pin FineLine BGA 400-Pin FineLine BGA Pitch (mm) 0.5 0.5 0.5 1.0 1.0 1.0 Area (mm2) 256 484 1,024 289 361 441 Length × width (mm × mm) 16×16 22×22 34.6×34.6 17×17 19×19 21×21 Table 1–4. Document Revision History Date and Document Version Changes Made Summary of Changes May 2008 v1.5 Minor textual and style changes. — January 2007 v1.4 Added document revision history. — August 2005 v1.3 Minor updates. — October 2003 v1.2 Added 64-bit PCI support information. — September 2003 v1.1 ● Updated LVDS data rates to 640 Mbps from 311 Mbps. ● Updated RSDS feature information. — May 2003 v1.0 Added document to Cyclone Device Handbook. — |
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