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5AGXMA3G627I3ES Datasheet(PDF) 4 Page - Altera Corporation |
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5AGXMA3G627I3ES Datasheet(HTML) 4 Page - Altera Corporation |
4 / 37 page Description Feature • 1.6 Gbps LVDS receiver and transmitter • 800 MHz/1.6 Gbps external memory interface • On-chip termination (OCT) • 3.3 V support 1 FPGA General-purpose I/Os (GPIOs) Memory interfaces with low latency: • Hard memory controller-up to 1.066 Gbps • Soft memory controller-up to 1.6 Gbps External Memory Interface • 600 Mbps to 12.5 Gbps integrated transceiver speed • Less than 105 mW per channel at 6 Gbps, less than 165 mW per channel at 10 Gbps, and less than 170 mW per channel at 12.5 Gbps • Transmit pre-emphasis and receiver equalization • Dynamic partial reconfiguration of individual channels • Physical medium attachment (PMA) with soft PCS that supports 9.8304 Gbps CPRI (Arria V GT and ST only) • PMA with hard PCS that supports up to 9.8 Gbps CPRI (Arria V GZ only) • Hard PCS that supports 10GBASE-R and 10GBASE-KR (Arria V GZ only) Low-power high-speed serial interface • Dual-core ARM Cortex-A9 MPCore processor-up to 800 MHz maximum frequency with support for symmetric and asymmetric multiprocessing • Interface peripherals—10/100/1000 Ethernet media access control (EMAC), USB 2.0 On-The-GO (OTG) controller, quad serial peripheral interface (QSPI) flash controller, NAND flash controller, Secure Digital/MultiMediaCard (SD/MMC) controller, UART, serial peripheral interface (SPI), I2C interface, and up to 85 HPS GPIO interfaces • System peripherals—general-purpose timers, watchdog timers, direct memory access (DMA) controller, FPGA configuration manager, and clock and reset managers • On-chip RAM and boot ROM • HPS–FPGA bridges—include the FPGA-to-HPS, HPS-to-FPGA, and lightweight HPS-to-FPGA bridges that allow the FPGA fabric to issue transactions to slaves in the HPS, and vice versa • FPGA-to-HPS SDRAM controller subsystem—provides a configurable interface to the multiport front end (MPFE) of the HPS SDRAM controller • ARM CoreSight ™ JTAG debug access port, trace port, and on-chip trace storage HPS (Arria V SX and ST devices only) • Tamper protection-comprehensive design protection to protect your valuable IP investments • Enhanced advanced encryption standard (AES) design security features • CvP • Partial and dynamic reconfiguration of the FPGA • Active serial (AS) x1 and x4, passive serial (PS), JTAG, and fast passive parallel (FPP) x8, x16, and x32 (Arria V GZ) configuration options • Remote system upgrade Configuration 1 Arria V GZ devices support 3.3 V with a 3.0 V V CCIO. Arria V Device Overview Altera Corporation Feedback AV-51001 Summary of Arria V Features 4 2013.05.06 |
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