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IR3725MTRPBF Datasheet(PDF) 5 Page - International Rectifier |
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IR3725MTRPBF Datasheet(HTML) 5 Page - International Rectifier |
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5 / 19 page  IR3725 Data Sheet Page 5 of 19 www.irf.com 2011_11_16 ADDR PIN The ADDR pin is an input that establishes the serial bus address. Valid addresses are selected by grounding, floating, or wiring to VDD the ADDR pin. Table 1, “User Selectable Addresses”, provides a mapping of possible selections. Bypass this pin to GND with a high quality ceramic capacitor when floated. Table 1 User selectable addresses ADDR pin configuration Bus Address Low b’1110 000 Open b’1110 010 High b’1110 110 EXTCLK This pin is a Schmitt trigger input for an optional externally provided square wave clock. The duty ratio of this externally provided clock, if used, shall be between 40% and 60%. If no external clock is connected, the internal clock will be used. Connect this pin to GND if no external clock is used. SCL SCL is the serial bus clock and is capable of functioning with a rate as low as 10 kHz. It will continue to function as the rate is increased to 400 kHz. This device is considered a slave, and therefore uses the SCL as an input only. SDA SDA is monitored as data input during master to slave transactions, and is driven as data output during slave to master transactions as indicated in the Packet Protocol section to follow. |
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