Dual Output Digital Multi-Phase Controller

IR3564A

IR3570A

August 9, 2012 | FINAL | Produc t Brief | V2.04

1

FEATURES

 Dual output 4+1 and 3+2 phase PWM Controllers

 Easiest layout and fewest pins in the industry

 Fully supports AMD® SVI1 & SVI2 with dual OCP

and Intel® VR12 & VR12.5

 Overclocking & Gaming Mode

 Switching frequency from 200kHz to 2MHz

per phase

 IR Efficiency Shaping Features including

Dynamic Phase Control and Automatic Power

State Switching

 Programmable 1-phase or 2-phase operation for

Light Loads and Active Diode Emulation for Very

Light Loads

 IR Adaptive Transient Algorithm (ATA) on both

loops minimizes output bulk capacitors and

system cost

 Auto-Phase Detection with auto-compensation

 Per-Loop Fault Protection: OVP, UVP, OCP,

OTP, CFP

 I2C/SMBus/PMBus system interface for telemetry

of Temperature, Voltage, Current & Power for

both loops

 Multiple Time Programming (MTP) with

integrated charge pump for easy custom

configuration

 Compatible with IR ATL and 3.3V tri-state Drivers

 +3.3V supply voltage; -40°C to 85°C ambient

operation

 Pb-Free, RoHS, 5x5mm, 40-pin, 0.4mm pitch QFN

BASIC APPLICATION

PWM1

12V

VOUT1

ISEN1

IRTN1

3.3V

SVD

ENABLE

ENABLE

SVC

IR3570A

VR_RDY_L1

SVT/ALERT#

VR_HOT#

PWM3

ISEN3

IRTN3

PWM1_L2

ISEN1_L2

IRTN1_L2

Power

Stage 4

..

.

VCC

PWM2_L2

ISEN2_L2

IRTN2_L2

Power

Stage 3

Power

Stage 1

VOUT2

VR_RDY_L2

VR_RDY_L1

VR_RDY_L2

VR_HOT#

SVD

SVC

SVT/ALERT#

Power

Stage 5

Figure 1: IR3564A/70A Basic Application Circuit

DESCRIPTION

The IR3564A/70A is a dual-loop digital multi-phase buck

controller designed for CPU voltage regulation and is fully

compliant with AMD® SVI1 & SVI2 and Intel® VR12 & VR12.5

specifications.

The IR3564A/70A includes IR’s Efficiency Shaping Technology

to deliver exceptional efficiency at minimum cost across the

entire load range. IR’s Dynamic Phase Control adds/drops

active phases based upon load current and can be configured

to enter 1-phase operation and diode emulation mode

automatically or by command.

IR’s unique Adaptive Transient Algorithm (ATA), based on

proprietary non-linear digital PWM algorithms, minimizes

output bulk capacitors and Multiple Time Programmable

(MTP) storage saves pins and enables a small package size.

Device configuration and fault parameters are easily defined

using the IR Digital Power Design Center (DPDC) GUI and

stored in on-chip MTP.

The IR3564A/70A provides extensive OVP, UVP, OCP and OTP

fault protection and includes thermistor based temperature

sensing with VRHOT signal.

The IR3564A/70A includes numerous features like register

diagnostics for fast design cycles and platform differentiation,

simplifying VRD design and enabling fastest time-to-market

(TTM) with “set-and-forget” methodology.

APPLICATIONS

 AMD® SVI1 & SVI2, Intel® VR12 & VR12.5 based systems

 Desktop & Notebook CPU VRs

 GPU & Memory VRs

PIN DIAGRAM

PWM1_L2

VRTN

RCSM

VSEN

PWRGD/

VRDY1

RCSP

TSEN1

PWM3

V18A

RRES

VCC

PWM2

PWM1

RCSM_L2

RCSP_L2

PWROK/EN_L2/

INMODE

VRDY2

VRTN_L2

VSEN_L2

1

2

7

8

5

6

3

4

10

9

30

29

24

23

26

25

28

27

21

22

41 GND

IR3570A/IR3564A

40 Pin 5x5 QFN

Top View

12

16

14

19

13

17

15

20

18

11

39

35

37

32

38

34

36

31

33

40

1 = IR3570A

2 = IR3564A

Figure 2: IR3564A/70A Package Top View