IR1150(S)/IR1150I(S)(PbF)

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8

Detailed Pin Description

COM: Ground

This is the ground potential pin of the integrated control

circuit. All internal devices are referenced to this point.

The output voltage of the boost converter is sensed via a

resistive divider and fed into this pin, which is the inverting

input of the output voltage error amplifier. The impedance

of the divider string must be low enough so as to not

introduce substantial error due to the input bias currents of

the amplifier, yet high enough so as to minimize power

dissipation. A typical value of external divider impedance

is 1MΩ.

The error amplifier is a transconductance type which yields

high output impedance, thus increasing the noise immunity

of the error amplifier output. This also eliminates input

divider string interaction with compensation feedback

capacitors and reducing the loading of divider string due to

a low impedance output of the amplifier.

COMP: Voltage Loop Compensation

External circuitry from this pin to ground compensates the

system voltage loop and soft start time. This is the output

of the voltage error amplifier. This pin will be discharged

via internal resistance when a fault mode occurs.

GATE: Gate Drive Output

This is the gate drive output of the IC. Drive voltage is

internally limited and provides ±1.5A peak with matched

rise and fall times.

FREQ: Frequency Set

This is the user programmable frequency pin. An

external resistor from this pin to the COM pin pro-

grams the frequency. The operational switching

frequency range for the device is 50kHz – 200kHz.

ISNS: Current Sense input

This pin is the inverting Current Sense Input & Peak

Current Limit. The voltage at this pin is the negative

voltage drop, sensed across the system current sense

resistor, representing the inductor current.

This voltage is fed into the Peak Current Limit protection

comparator with threshold around -1V. This protection

circuit incorporates a leading edge blanking circuit

following the comparator to improve noise immunity of the

protection process.

The current sense signal is also fed into the current sense

amplifier. The signal is amplified, filtered of high frequency

noise and then injected into a summing node where it is

The signal on this pin must be previously filtered with an

RC cell to provide additional noise immunity. The input

impedance of this pin is 5kΩ .

This is the supply voltage pin of the IC and it is monitored

by the under voltage lockout circuit. It is possible to turn

off the IC by pulling this pin below the minimum turn off

threshold voltage, without damage to the IC.

To prevent noise problems, a bypass ceramic capacitor

connected to VCC and COM should be placed as close as

possible to the IR1150.

This pin is not internally clamped, therefore damage will

occur if the maximum voltage is exceeded.

OVP/EN: Over Voltage Protection / Enable

This pin is the input to the over voltage protection

comparator

the

threshold

of

which

is

internally

programmed to 105.5% of VREF.

A resistive divider feeds this pin from the output volt-age

to COM and inhibits the gate drive whenever the threshold

is exceeded. Normal operation resumes when the voltage

level on this pin decreases to below the pin threshold.

This pin is also used to activate “sleep” mode by pulling

the voltage level below 0.62V (typ).