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IP1827 Datasheet(PDF) 17 Page - International Rectifier |
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IP1827 Datasheet(HTML) 17 Page - International Rectifier |
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17 / 39 page  iP1827 Highly Integrated 25A Single‐input Voltage, Synchronous Buck Regulator March 5, 2012 | V1.4 17 97599 In applications where only local sensing is required for feedback, the remote voltage sensing pins of the iP1827 may be dedicated to sensing the output for power good indication and overvoltage protection. POWER GOOD OUTPUT AND OVER‐VOLTAGE PROTECTION The IC continually monitors the output voltage via output of the remote sense amplifier (Voso pin). The Voso voltage forms an input to a window comparator whose upper and lower thresholds are 0.7V and 0.51V respectively. Hence, the Power Good signal is flagged when the Voso pin voltage is within PGood window, i.e., between 0.51V and 0.69V, as shown in Figure 12a. The PGood pin is open drain and it needs to be externally pulled high. High state indicates that output is in regulation. Figure 12a also shows the PGood timing diagram with a 256 cycle delay between the Voso voltage entering within the thresholds defined by the PGood window and PGood going high If the output voltage exceeds the over voltage threshold 0.7V, an over voltage trip signal is asserted; this will turn off the high side driver and turn on the low side driver until the Voso voltage drops below the 0.7V threshold. Both drivers are then turned off until a reset is performed by cycling Vcc (or PVcc/Enable) or until another OVP event occurs turning on the low side driver again. Figure 12b shows the response in over‐voltage condition. SS 0 0 0 PGD 256/Fs Voso 0.2V 0.8V 0.51V 0.7V 256/Fs Figure 12a: iP1827 Power Good Signal Timing Diagram HDrv 0 0 0 LDrv Voso 0.7V SS 0 0 PGood 0.6V Figure 12b: iP1827 Signal Timing for OVP BODY BRAKING TM The Body Braking feature of the iP1827 allows improved transient response to step‐down load transients. A severe step‐down load transient would cause an overshoot in the output voltage and drive the Comp pin voltage down until control saturation occurs demanding 0% duty cycle, and the PWM input to the Control FET driver is kept OFF. When the first such skipped pulse occurs, the iP1827 enters the Body Braking mode, wherein the Sync FET is also turned OFF. The inductor current then decays by freewheeling through the body diode of the Sync FET. Thus, with Body Braking, the forward voltage drop of the body diode provides an additional voltage to discharge the inductor current faster to the light load value as shown in equations 4 and 5 below: , , (5) braking body without (4) braking body with L V dt di L V V dt di o L D o L where VD= forward voltage drop of the body diode of the Sync FET. The Body Braking mechanism is kept OFF during pre‐bias operation. Also, in the event of an extremely severe load step‐down transient causing an OVP, the Body Brake is overridden by the OVP latch, which turns on the Sync FET. |
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