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CRCW06035K11FKEA Datasheet(PDF) 11 Page - Vishay Siliconix |
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CRCW06035K11FKEA Datasheet(HTML) 11 Page - Vishay Siliconix |
11 / 19 page SiP12107 www.vishay.com Vishay Siliconix S12-0412-Rev. B, 20-Feb-12 11 Document Number: 63395 THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 OPERATIONAL DESCRIPTION Device Overview SiP12107 is a high-efficiency monolithic synchronous buck regulator capable of delivering up to 3 A continuous current. The device has programmable switching frequency up to 4 MHz. The control scheme is based on current-mode constant-on-time architecture, which delivers fast transient response and minimizes external components. Thanks to the internal current ramp information, no high-ESR output bulk or virtual ESR network is required for the loop stability. This device also incorporates Power-Saving feature by enabling diode emulation mode and frequency foldback as load decrease. SiP12107 has a full set of protection and monitoring features: - Over current protection in pulse-by-pulse mode - Output over voltage protection - Output under voltage protection with device latch - Over temperature protection with hysteresis - Dedicated enable pin for easy power sequencing - Power Good open drain output This device is available in MLPQ 3 x 3-16L package to deliver high power density and minimize PCB area. Power Stage SiP12107 integrates a high-performance power stage with a ~ 64 m p-channel MOSFET and a ~ 33 m n-channel MOSFET. The MOSFETs are optimized to achieve 95 % efficiency at 2 MHz switching frequency. The power input voltage (VIN) can go up to 5.5 V and down as low as 2.8 V for the power conversion. The logic bias voltage (AVIN) ranges from 2.8 V to 5.5 V. PWM Control Mechanism SiP12107 employs a state-of-the-art current-mode COT control mechanism. During steady-state operation, output voltage is compared with internal reference (0.6 V typ.) and the amplified error signal (VCOMP) is generated on the COMP pin. In the meantime, inductor valley current is sensed, and its slope (Isense) is converted into a voltage signal (Vcurrent) to be compared with VCOMP. Once Vcurrent is lower than VCOMP, a single shot on-time is generated for a fixed time programmed by the external RON. Figure 4 illustrates the basic block diagram for CM-COT architecture and figure 5 demonstrates the basic operational principle: Fig. 4 - CM-COT Block Diagram HG LG HG LG OTA - + Bandgap V ref V OUT Current Mirror LS FET PWM COMPARATOR - + - + V IN I-AMP ON-TIME Generator V OUT V IN R ON Control Logic & MOSFET Driver Vcomp Isense Vcurrent |
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