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ICS9ZX21901CKLFT Datasheet(PDF) 8 Page - Integrated Device Technology |
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ICS9ZX21901CKLFT Datasheet(HTML) 8 Page - Integrated Device Technology |
8 / 16 page IDT® 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI 1648H- 12/08/11 9ZX21901C 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI 8 Electrical Characteristics - Phase Jitter Parameters TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Notes tjphPCIeG1 PCIe Gen 1 39 86 ps (p-p) 1,2,3 PCIe Gen 2 Lo Band 10kHz < f < 1.5MHz 1.1 3 ps (rms) 1,2 PCIe Gen 2 High Band 1.5MHz < f < Nyquist (50MHz) 2.6 3.1 ps (rms) 1,2 tjphPCIeG3 PCIe Gen 3 (PLL BW of 2-4MHz, CDR = 10MHz) 0.6 1 ps (rms) 1,2,4 QPI & SMI (100MHz or 133MHz, 4.8Gb/s, 6.4Gb/s 12UI) 0.36 0.5 ps (rms) 1,5 QPI & SMI (100MHz, 8.0Gb/s, 12UI) 0.23 0.3 ps (rms) 1,5 QPI & SMI (100MHz, 9.6Gb/s, 12UI) 0.18 0.2 ps (rms) 1,5 tjphPCIeG1 PCIe Gen 1 4 10 ps (p-p) 1,2,3 PCIe Gen 2 Lo Band 10kHz < f < 1.5MHz 0.25 0.3 ps (rms) 1,2,6 PCIe Gen 2 High Band 1.5MHz < f < Nyquist (50MHz) 0.57 0.7 ps (rms) 1,2,6 tjphPCIeG3 PCIe Gen 3 (PLL BW of 2-4MHz, CDR = 10MHz) 0.20 0.3 ps (rms) 1,2,4,6 QPI & SMI (100MHz or 133MHz, 4.8Gb/s, 6.4Gb/s 12UI) 0.22 0.3 ps (rms) 1,5,6 QPI & SMI (100MHz, 8.0Gb/s, 12UI) 0.08 0.1 ps (rms) 1,5,6 QPI & SMI (100MHz, 9.6Gb/s, 12UI) 0.08 0.1 ps (rms) 1,5,6 1 Applies to all outputs. 6 For RMS figures, additive jitter is calculated by solving the following equation: (Additive jitter)^2 = (total jittter)^2 - (input jitter)^2 5 Calculated from Intel-supplied Clock Jitter Tool v 1.6.3 Jitter, Phase tjphPCIeG2 tjphQPI_SMI 2 See http://www.pcisig.com for complete specs 3 Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12. 4 Subject to final radification by PCI SIG. Additive Phase Jitter, Bypass mode tjphPCIeG2 tjphQPI_SMI Power Management Table Outputs CKPWRGD_PD# DIF_IN/ DIF_IN# SMBus EN bit OE# Pin DIF(5:12)/ DIF(5:12)# Other DIF/ DIF# DFB_OUT/ DFB_OUT# 0X X X Hi-Z 1 Hi-Z 1 Hi-Z 1 OFF 0X Hi-Z 1 Hi-Z 1 Running ON 1 0 Running Running Running ON 11 Hi-Z 1 Running Running ON NOTE: 1. Due to external pull down resistors, HI-Z results in Low/Low on the True/Complement outputs Running Control Bits/Pins PLL State Inputs 1 |
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