MCIMX6D1EYM08AC datasheet(98/165 Pages) FREESCALE

Part #	MCIMX6D1EYM08AC

Description	i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors

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Manufacturer	FREESCALE [Freescale Semiconductor, Inc]

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98 / 165 page

i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2.3

98

Freescale Semiconductor

Electrical Characteristics

A frame starts with a rising edge on IPU2_CSIx_VSYNC (all the timings correspond to straight polarity

of the corresponding signals). Then IPU2_CSIx_HSYNC goes to high and hold for the entire line. Pixel

clock is valid as long as IPU2_CSIx_HSYNC is high. Data is latched at the rising edge of the valid pixel

clocks. IPU2_CSIx_HSYNC goes to low at the end of line. Pixel clocks then become invalid and the CSI

stops receiving data from the stream. For the next line, the IPU2_CSIx_HSYNC timing repeats. For the

next frame, the IPU2_CSIx_VSYNC timing repeats.

4.11.10.2.3 Non-Gated Clock Mode

The timing is the same as the gated-clock mode (described in Section 4.11.10.2.2, “Gated Clock Mode,”)

except for the IPU2_CSIx_HSYNC signal, which is not used (see Figure 66). All incoming pixel clocks

are valid and cause data to be latched into the input FIFO. The IPU2_CSIx_PIX_CLK signal is inactive

(states low) until valid data is going to be transmitted over the bus.

Figure 66. Non-Gated Clock Mode Timing Diagram

The timing described in Figure 66 is that of a typical sensor. Some other sensors may have a slightly

different timing. The CSI can be programmed to support rising/falling-edge triggered

IPU2_CSIx_VSYNC; active-high/low IPU2_CSIx_HSYNC; and rising/falling-edge triggered

IPU2_CSIx_PIX_CLK.

IPU2_CSIx_VSYNC

IPU2_CSIx_PIX_CLK

IPU2_CSIx_DATA_EN[19:0]

invalid

1st byte

n+1th frame

invalid

1st byte

nth frame

Start of Frame

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