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MCIMX6D5DVT08AC Datasheet(PDF) 31 Page - Freescale Semiconductor, Inc |
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MCIMX6D5DVT08AC Datasheet(HTML) 31 Page - Freescale Semiconductor, Inc |
31 / 165 page Electrical Characteristics i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2.3 Freescale Semiconductor 31 4.2.2 Power-Down Sequence No special restrictions for i.MX 6Dual/6Quad SoC. 4.2.3 Power Supplies Usage • All I/O pins should not be externally driven while the I/O power supply for the pin (NVCC_xxx) is OFF. This can cause internal latch-up and malfunctions due to reverse current flows. For information about I/O power supply of each pin, see “Power Group” column of Table 101, "21 x 21 mm Functional Contact Assignments," on page 147. • When the SATA interface is not used, the SATA_VP and SATA_VPH supplies should be grounded. The input and output supplies for rest of the ports (SATA_REXT, SATA_PHY_RX_N, SATA_PHY_RX_P, and SATA_PHY_TX_N) can be left floating. It is recommended not to turn OFF the SATA_VPH supply while the SATA_VP supply is ON, as it may lead to excessive power consumption. If boundary scan test is used, SATA_VP and SATA_VPH must remain powered. • When the PCIE interface is not used, the PCIE_VP, PCIE_VPH, and PCIE_VPTX supplies should be grounded. The input and output supplies for rest of the ports (PCIE_REXT, PCIE_RX_N, PCIE_RX_P, PCIE_TX_N, and PCIE_TX_P) can be left floating. It is recommended not to turn the PCIE_VPH supply OFF while the PCIE_VP supply is ON, as it may lead to excessive power consumption. If boundary scan test is used, PCIE_VP, PCIE_VPH, and PCIE_VPTX must remain powered. 4.3 Integrated LDO Voltage Regulator Parameters Various internal supplies can be powered ON from internal LDO voltage regulators. All the supply pins named *_CAP must be connected to external capacitors. The onboard LDOs are intended for internal use only and should not be used to power any external circuitry. See the i.MX 6Dual/6Quad reference manual (IMX6DQRM) for details on the power tree scheme recommended operation. NOTE The *_CAP signals should not be powered externally. These signals are intended for internal LDO or LDO bypass operation only. 4.3.1 Digital Regulators (LDO_ARM, LDO_PU, LDO_SOC) There are three digital LDO regulators (“Digital”, because of the logic loads that they drive, not because of their construction). The advantages of the regulators are to reduce the input supply variation because of their input supply ripple rejection and their on die trimming. This translates into more voltage for the die producing higher operating frequencies. These regulators have three basic modes. • Bypass. The regulation FET is switched fully on passing the external voltage, DCDC_LOW, to the load unaltered. The analog part of the regulator is powered down in this state, removing any loss other than the IR drop through the power grid and FET. • Power Gate. The regulation FET is switched fully off limiting the current draw from the supply. The analog part of the regulator is powered down here limiting the power consumption. |
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