Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.COM

X  

PD46365182BF1-E33Y-EQ1 Datasheet(PDF) 9 Page - Renesas Technology Corp

Part # PD46365182BF1-E33Y-EQ1
Description  36M-BIT QDRTM II SRAM 2-WORD BURST OPERATION
Download  36 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

PD46365182BF1-E33Y-EQ1 Datasheet(HTML) 9 Page - Renesas Technology Corp

Back Button PD46365182BF1-E33Y-EQ1 Datasheet HTML 5Page - Renesas Technology Corp PD46365182BF1-E33Y-EQ1 Datasheet HTML 6Page - Renesas Technology Corp PD46365182BF1-E33Y-EQ1 Datasheet HTML 7Page - Renesas Technology Corp PD46365182BF1-E33Y-EQ1 Datasheet HTML 8Page - Renesas Technology Corp PD46365182BF1-E33Y-EQ1 Datasheet HTML 9Page - Renesas Technology Corp PD46365182BF1-E33Y-EQ1 Datasheet HTML 10Page - Renesas Technology Corp PD46365182BF1-E33Y-EQ1 Datasheet HTML 11Page - Renesas Technology Corp PD46365182BF1-E33Y-EQ1 Datasheet HTML 12Page - Renesas Technology Corp PD46365182BF1-E33Y-EQ1 Datasheet HTML 13Page - Renesas Technology Corp Next Button
Zoom Inzoom in Zoom Outzoom out
 9 / 36 page
background image
μPD46365092B, μPD46365182B, μPD46365362B
R10DS0089EJ0400 Rev.4.00
Page 9 of 35
Nov 09, 2012
Power-On Sequence in QDR II SRAM
QDR II SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.
The following timing charts show the recommended power-on sequence.
The following power-up supply voltage application is recommended: VSS, VDD, VDDQ, VREF, then VIN. VDD and VDDQ
can be applied simultaneously, as long as VDDQ does not exceed VDD by more than 0.5 V during power-up. The
following power-down supply voltage removal sequence is recommended: VIN, VREF, VDDQ, VDD, VSS. VDD and VDDQ
can be removed simultaneously, as long as VDDQ does not exceed VDD by more than 0.5 V during power-down.
Power-On Sequence
Apply power and tie DLL# to HIGH.
Apply VDDQ before VREF or at the same time as VREF.
Provide stable clock for more than 20
μs to lock the PLL.
Continuous min.4 NOP(R# = high) cycles are required after PLL lock up is done.
PLL Constraints
The PLL uses K clock as its synchronizing input and the input should have low phase jitter which is specified as
TKC var. The PLL can cover 120 MHz as the lowest frequency. If the input clock is unstable and the PLL is
enabled, then the PLL may lock onto an undesired clock frequency.
Power-On Waveforms
20
μs or more
Stable Clock
VDD/VDDQ Stable (< ±0.1 V DC per 50 ns)
VDD/VDDQ
Clock
Unstable Clock
Normal Operation
Start
DLL#
Fix HIGH (or tied to VDDQ)
R#
4 Times NOP


Similar Part No. - PD46365182BF1-E33Y-EQ1

ManufacturerPart #DatasheetDescription
logo
Renesas Technology Corp
PD46365184B RENESAS-PD46365184B Datasheet
598Kb / 39P
   36M-BIT QDRTM II SRAM 4-WORD BURST OPERATION
PD46365184BF1-E33-EQ1 RENESAS-PD46365184BF1-E33-EQ1 Datasheet
598Kb / 39P
   36M-BIT QDRTM II SRAM 4-WORD BURST OPERATION
PD46365184BF1-E33-EQ1-A RENESAS-PD46365184BF1-E33-EQ1-A Datasheet
598Kb / 39P
   36M-BIT QDRTM II SRAM 4-WORD BURST OPERATION
PD46365184BF1-E33Y-EQ1 RENESAS-PD46365184BF1-E33Y-EQ1 Datasheet
598Kb / 39P
   36M-BIT QDRTM II SRAM 4-WORD BURST OPERATION
PD46365184BF1-E33Y-EQ1-A RENESAS-PD46365184BF1-E33Y-EQ1-A Datasheet
598Kb / 39P
   36M-BIT QDRTM II SRAM 4-WORD BURST OPERATION
More results

Similar Description - PD46365182BF1-E33Y-EQ1

ManufacturerPart #DatasheetDescription
logo
Renesas Technology Corp
UPD44325092B RENESAS-UPD44325092B Datasheet
393Kb / 36P
   36M-BIT QDRTM II SRAM 2-WORD BURST OPERATION
August 11, 2011
UPD46365092B RENESAS-UPD46365092B Datasheet
619Kb / 36P
   36M-BIT QDRTM II SRAM 2-WORD BURST OPERATION
Nov 09, 2012
PD46365092B RENESAS-PD46365092B_15 Datasheet
619Kb / 36P
   36M-BIT QDRTM II SRAM 2-WORD BURST OPERATION
PD44325092B RENESAS-PD44325092B_15 Datasheet
416Kb / 36P
   36M-BIT QDRTM II SRAM 2-WORD BURST OPERATION
UPD46365084B RENESAS-UPD46365084B Datasheet
598Kb / 39P
   36M-BIT QDRTM II SRAM 4-WORD BURST OPERATION
Nov 09 2012
PD46365084B RENESAS-PD46365084B_15 Datasheet
598Kb / 39P
   36M-BIT QDRTM II SRAM 4-WORD BURST OPERATION
UPD44325084B RENESAS-UPD44325084B Datasheet
446Kb / 40P
   36M-BIT QDRTM II SRAM 4-WORD BURST OPERATION
September 12, 2011
PD46365084B RENESAS-PD46365084B Datasheet
598Kb / 39P
   36M-BIT QDRTM II SRAM 4-WORD BURST OPERATION
PD44325084B RENESAS-PD44325084B_15 Datasheet
458Kb / 40P
   36M-BIT QDRTM II SRAM 4-WORD BURST OPERATION
PD46364092B RENESAS-PD46364092B Datasheet
640Kb / 36P
   36M-BIT DDR II SRAM 2-WORD BURST OPERATION
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com