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R1Q5A7218AB Datasheet(PDF) 10 Page - Renesas Technology Corp |
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R1Q5A7218AB Datasheet(HTML) 10 Page - Renesas Technology Corp |
10 / 36 page R1Q4A7236ABB / R1Q4A7218ABB Series Rev. 0.11 : 2013.01.15 PAGE:10 Common DLL/PLL Constraints 1. DLL/PLL uses K clock as its synchronizing input. The input should have low phase jitter which is specified as tKC var. 2. The lower end of the frequency at which the DLL/PLL can operate is 120 MHz. (Please refer to AC Characteristics table for detail.) 3. When the operating frequency is changed or /DOFF level is changed, setup cycles are required again. Programmable Output Impedance 1. Output buffer impedance can be programmed by terminating the ZQ ball to V SS through a precision resistor (RQ). The value of RQ is five times the output impedance desired. The allowable range of RQ to guarantee impedance matching with a tolerance of 15% is 250 Ω typical. The total external capacitance of ZQ ball must be less than 7.5 pF. R10DS0166EJ0011 |
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