μPD46184095B, μPD46184185B

R10DS0115EJ0200 Rev.2.00

Page 8 of 34

Nov 09, 2012

Power-On Sequence in DDR II SRAM

DDR II SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.

The following timing charts show the recommended power-on sequence.

Power-On Sequence

Apply power and tie DLL# to HIGH.

Provide stable clock for more than 20

μs to lock the PLL.

Continuous min.4 NOP(LD# = high) cycles are required after PLL lock up is done.

PLL Constraints

The PLL uses K clock as its synchronizing input and the input should have low phase jitter which is specified as

TKC var. The PLL can cover 120 MHz as the lowest frequency. If the input clock is unstable and the PLL is

enabled, then the PLL may lock onto an undesired clock frequency.

Power-On Waveforms

20

μs or more

Stable Clock

Clock

Unstable Clock

Normal Operation

Start

DLL#

LD#

4 Times NOP