μPD46184095B, μPD46184185B

R10DS0115EJ0200 Rev.2.00

Page 9 of 34

Nov 09, 2012

Truth Table

Operation

LD# R, W#

CLK

D or Q

WRITE cycle

L

L

L

→ H

Data in

Load address, input write data on

Input data

D(A+0)

D(A+1)

consecutive K and K# rising edge

Input clock

K(t+1)

↑

K#(t+1)

↑

READ cycle

L

H

L

→ H

Data out

Load address, read data on

Output data

Q(A+0)

Q(A+1)

consecutive C and C# rising edge

Output clock

C#(t+1)

↑

C(t+2)

↑

NOP (No operation)

H

×

L

→ HD = ×, Q = High-Z

Clock stop

×

×

Stopped

Previous state

Remarks 1. H : HIGH, L : LOW,

× : don’t care, ↑ : rising edge.

2. Data inputs are registered at K and K# rising edges. Data outputs are delivered at C and C# rising edges

except if C and C# are HIGH then Data outputs are delivered at K and K# rising edges.

3. All control inputs in the truth table must meet setup/hold times around the rising edge (LOW to HIGH) of

K. All control inputs are registered during the rising edge of K.

4. This device contains circuitry that ensure the outputs to be in high impedance during power-up.

5. Refer to state diagram and timing diagrams for clarification.

6. It is recommended that K = K# = C = C# when clock is stopped. This is not essential but permits most

rapid restart by overcoming transmission line charging symmetrically.