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R5F56104WNBG Datasheet(PDF) 7 Page - Renesas Technology Corp |
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R5F56104WNBG Datasheet(HTML) 7 Page - Renesas Technology Corp |
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7 / 86 page  RX610 Group 1. Overview R01DS0097EJ0120 Rev.1.20 Page 7 of 84 Feb 20, 2013 1.3 Block Diagram Figure 1.2 shows a block diagram of the RX610 Group. ROM RAM RX CPU DTC DMAC External bus ICU BSC A/D converter × 4 channels (unit 3) A/D converter × 4 channels (unit 2) A/D converter × 4 channels (unit 1) A/D converter × 4 channels (unit 0) TMR × 2 channels (unit 1) TMR × 2 channels (unit 0) TPU × 6 channels (unit 1) TPU × 6 channels (unit 0) PPG (unit 1) PPG (unit 0) D/A converter × 2 channels CMT × 2 channels (unit 1) SCI × 7 channels WDT RIIC × 2 channels Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port A Port B Port C Port D Port E Clock generation circuit Data flash CRC CMT × 2 channels (unit 0) [Legend] ICU: Interrupt control unit DTC: Data transfer controller DMAC: DMA controller BSC: Bus controller WDT: Watchdog timer CRC: CRC (Cyclic Redundancy Check) calculator SCI: Serial communications interfaces TPU: 16-bit timer pulse unit PPG: Programmable pulse generator TMR: 8-bit timer CMT: Compare match timer RIIC: I2C bus interface Port F Port G Port H * Note: * Ports F and H are not included in the 144-pin LQFP package. Figure 1.2 Block Diagram |
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