Electronic Components Datasheet Search |
|
AD5305 Datasheet(PDF) 17 Page - Analog Devices |
|
AD5305 Datasheet(HTML) 17 Page - Analog Devices |
17 / 24 page Data Sheet AD5304/AD5314/AD5324 Rev. H | Page 17 of 24 AD5304/AD5314/AD5324 to 68HC11/68L11 Interface Figure 37 shows a serial interface between the AD5304/AD5314/ AD5324 and the 68HC11/68L11 microcontroller. SCK of the 68HC11/68L11 drives the SCLK of the AD5304/AD5314/AD5324, while the MOSI output drives the serial data line (DIN) of the DAC. The SYNC signal is derived from a port line (PC7). The setup conditions for the correct operation of this interface are as follows: the 68HC11/68L11 is configured so that its CPOL bit is a 0 and its CPHA bit is a 1. When data is being transmitted to the DAC, the SYNC line is taken low (PC7). When the 68HC11/68L11 is configured as above, data appearing on the MOSI output is valid on the falling edge of SCK. Serial data from the 68HC11/ 68L11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. Data is transmitted MSB first. To load data to the AD5304/ AD5314/AD5324, PC7 is left low after the first eight bits are transferred, a second serial write operation is performed to the DAC, and PC7 is taken high at the end of this procedure. AD5304/ AD5314/ AD5324* 68HC11/68L11* *ADDITIONAL PINS OMITTED FOR CLARITY. SCLK SCK DIN MOSI SYNC PC7 Figure 37. AD5304/AD5314/AD5324 to 68HC11/68L11 Interface AD5304/AD5314/AD5324 to 80C51/80L51 Interface Figure 38 shows a serial interface between the AD5304/AD5314/ AD5324 and the 80C51/80L51 microcontroller. The setup for the interface is as follows: TxD of the 80C51/80L51 drives SCLK of the AD5304/AD5314/AD5324, while RxD drives the serial data line of the part. The SYNC signal is again derived from a bit-programmable pin on the port. In this case, port line P3.3 is used. When data is to be transmitted to the AD5304/AD5314/ AD5324, P3.3 is taken low. The 80C51/80L51 transmits data only in 8-bit bytes; thus only eight falling clock edges occur in the transmit cycle. To load data to the DAC, P3.3 is left low after the first eight bits are transmitted, and a second write cycle is initiated to transmit the second byte of data. P3.3 is taken high following the completion of this cycle. The 80C51/80L51 outputs the serial data in a format that has the LSB first. The AD5304/ AD5314/AD5324 requires its data with the MSB as the first bit received. The 80C51/80L51 transmit routine takes this into account. AD5304/ AD5314/ AD5324* 80C51/80L51* *ADDITIONAL PINS OMITTED FOR CLARITY. SCLK TxD DIN RxD SYNC P3.3 Figure 38. AD5304/AD5314/AD5324 to 80C51/80L51 Interface AD5304/AD5314/AD5324 to MICROWIRE Interface Figure 39 shows an interface between the AD5304/AD5314/ AD5324 and any MICROWIRE-compatible device. Serial data is shifted out on the falling edge of the serial clock, SK, and is clocked into the AD5304/AD5314/AD5324 on the rising edge of SK, which corresponds to the falling edge of the DAC’s SCLK. AD5304/ AD5314/ AD5324* MICROWIRE* *ADDITIONAL PINS OMITTED FOR CLARITY. SCLK SK DIN SO SYNC CS Figure 39. AD5304/AD5314/AD5324 to MICROWIRE Interface |
Similar Part No. - AD5305 |
|
Similar Description - AD5305 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |