Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF Download HTML

AD5227 Datasheet(PDF) 4 Page - Analog Devices

Part No. AD5227
Description  64-Position Up/Down Control Digital Potentiometer
Download  16 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  AD [Analog Devices]
Homepage  http://www.analog.com
Logo 

AD5227 Datasheet(HTML) 4 Page - Analog Devices

 
Zoom Inzoom in Zoom Outzoom out
 4 / 16 page
background image
AD5227
Rev. B | Page 4 of
16
Parameter
Symbol
Conditions
Min
Typ1
Max
Unit
INTERFACE TIMING CHARACTERISTICS (applies to all parts6, 10)
Clock Frequency
fCLK
50
MHz
Input Clock Pulse Width
tCH, tCL
Clock level high or low
10
ns
CS to CLK Setup Time
tCSS
10
ns
CS Rise to CLK Hold Time
tCSH
10
ns
U/D to Clock Fall Setup Time
tUDS
10
ns
1 Typicals represent average readings at 25°C, VDD = 5 V.
2 Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3 NL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.
4 DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
5 Resistor Terminals A, B, W have no limitations on polarity with respect to each other.
6 Guaranteed by design and not subject to production test.
7 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
8 Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest
bandwidth. The highest R value results in the minimum overall power consumption.
9 All dynamic characteristics use VDD = V.
10 All input control voltages are specified with tR = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. Switching characteristics are measured using
VDD = 5 V.
INTERFACE TIMING DIAGRAMS
CS = LOW
U/D = HIGH
CLK
RWB
Figure 2. Increment RWB
CS = LOW
U/D = 0
CLK
RWB
Figure 3. Decrement RWB
1
0
1
0
1
0
CS
CLK
U/D
RWB
tS
tUDS
tCL
tCH
tCSS
tCSH
Figure 4. Detailed Timing Diagram (Only RWB Decrement Shown)


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16 


Datasheet Download




Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Alldatasheet API   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn