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MT47H64M8B6-25ELDTR Datasheet(PDF) 35 Page - Micron Technology |
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MT47H64M8B6-25ELDTR Datasheet(HTML) 35 Page - Micron Technology |
35 / 133 page Table 12: AC Operating Specifications and Conditions (Continued) Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: 1–5 apply to the entire table; VDDQ = 1.8V ±0.1V, VDD = 1.8V ±0.1V AC Characteristics -187E -25E -25 -3E -3 -37E -5E Units Notes Parameter Symbol Min Max Min Max Min Max Min Max Min Max Min Max Min Max Input setup time tISb 125 – 175 – 175 – 200 – 200 – 250 – 350 – ps 31, 33 Input hold time tIHb 200 – 250 – 250 – 275 – 275 – 375 – 475 – ps 31, 33 Input setup time tISa 325 – 375 – 375 – 400 – 400 – 500 – 600 – ps 31, 33 Input hold time tIHa 325 – 375 – 375 – 400 – 400 – 500 – 600 – ps 31, 33 Input pulse width tIPW 0.6 – 0.6 – 0.6 – 0.6 – 0.6 – 0.6 – 0.6 – tCK 18, 32 ACTIVATE-to- ACTIVATE delay, same bank tRC 54 – 55 – 55 – 54 – 55 – 55 – 55 – ns 18, 34, 51 ACTIVATE-to-READ or WRITE delay tRCD 13.125 – 12.5 – 15 – 12 – 15 – 15 – 15 – ns 18 ACTIVATE-to- PRECHARGE delay tRAS 40 70K 40 70K 40 70K 40 70K 40 70K 40 70K 40 70K ns 18, 34, 35 PRECHARGE period tRP 13.125 – 12.5 – 15 – 12 – 15 – 15 – 15 – ns 18, 36 PRE- CHARGE ALL period <1Gb tRPA 13.125 – 12.5 – 15 – 12 – 15 – 15 – 15 – ns 18, 36 ≥1Gb tRPA 15 – 15 – 17.5 15 18 18.75 20 ns 18, 36 ACTIVATE -to- ACTIVATE delay different bank x4, x8 tRRD 7.5 – 7.5 – 7.5 – 7.5 – 7.5 – 7.5 – 7.5 – ns 18, 37 x16 tRRD 10 – 10 – 10 – 10 – 10 – 10 – 10 – ns 18, 37 4-bank activate period ( ≥1Gb) x4, x8 tFAW 35 – 35 – 35 – 37.5 – 37.5 – 37.5 – 37.5 – ns 18, 38 x16 tFAW 45 – 45 – 45 – 50 – 50 – 50 – 50 – ns 18, 38 |
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