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MT47H64M8B6-25ELDTR Datasheet(PDF) 96 Page - Micron Technology |
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MT47H64M8B6-25ELDTR Datasheet(HTML) 96 Page - Micron Technology |
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96 / 133 page  Figure 47: READ Interrupted by READ T0 T1 T2 Don’t Care Transitioning Data T3 T4 T5 T6 Command READ1 NOP2 NOP2 Valid Valid Valid READ3 Valid Valid Valid T7 T8 T9 CK CK# CL = 3 (AL = 0) tCCD Address Valid4 Valid4 CL = 3 (AL = 0) DQ DO DO DO DO DO DO DO DO DO DO DO DO A10 Valid5 DQS, DQS# Notes: 1. BL = 8 required; auto precharge must be disabled (A10 = LOW). 2. NOP or COMMAND INHIBIT commands are valid. PRECHARGE command cannot be is- sued to banks used for READs at T0 and T2. 3. Interrupting READ command must be issued exactly 2 × tCK from previous READ. 4. READ command can be issued to any valid bank and row address (READ command at T0 and T2 can be either same bank or different bank). 5. Auto precharge can be either enabled (A10 = HIGH) or disabled (A10 = LOW) by the in- terrupting READ command. 6. Example shown uses AL = 0; CL = 3, BL = 8, shown with nominal tAC, tDQSCK, and tDQSQ. Figure 48: READ-to-WRITE CK CK# T0 T1 T2 Don’t Care Transitioning Data T3 T4 T5 T6 T7 T8 T9 T10 T11 AL = 2 CL = 3 RL = 5 WL = RL - 1 = 4 tRCD = 3 Command ACT n NOP NOP NOP NOP NOP NOP READ n NOP NOP NOP WRITE DQS, DQS# DQ DO n DO n + 1 DO n + 2 DO n + 3 DI n DI n + 1 DI n + 2 DI n + 3 Notes: 1. BL = 4; CL = 3; AL = 2. 2. Shown with nominal tAC, tDQSCK, and tDQSQ. READ with Precharge A READ burst may be followed by a PRECHARGE command to the same bank, provided auto precharge is not activated. The minimum READ-to-PRECHARGE command spac- ing to the same bank has two requirements that must be satisfied: AL + BL/2 clocks and tRTP. tRTP is the minimum time from the rising clock edge that initiates the last 4-bit prefetch of a READ command to the PRECHARGE command. For BL = 4, this is the time from the actual READ (AL after the READ command) to PRECHARGE command. For BL = 8, this is the time from AL + 2 × CK after the READ-to-PRECHARGE command. Fol- 512Mb: x4, x8, x16 DDR2 SDRAM READ PDF: 09005aef82f1e6e2 512MbDDR2.pdf - Rev. T 2/12 EN 96 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2004 Micron Technology, Inc. All rights reserved. |
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