10

Integrated Silicon Solution, Inc. — www.issi.com

Rev. I

08/10/09

IS61WV5128ALL/ALS, IS61WV5128BLL/BLS

IS64WV5128BLL/BLS

-20 ns

-25 ns

-35 ns

Symbol

Parameter

Min. Max.

Min. Max.

Min. Max.

Unit

Read Cycle Time

20

—

25

—

35

—

ns

Address Access Time

—

20

—

25

—

35

ns

Output Hold Time

2.5

—

4

—

4

—

ns

CE

Access Time

—

20

—

25

—

35

ns

OE

Access Time

—

8

—

12

—

15

ns

OE

to High-Z Output

0

8

0

8

0

10

ns

OE

to Low-Z Output

0

—

0

—

0

—

ns

CE

to High-Z Output

0

8

0

8

0

10

ns

CE

to Low-Z Output

3

—

10

—

10

—

ns

Power Up Time

0

—

0

—

0

—

ns

Power Down Time

—

20

—

25

—

35

ns

Notes:

1. Test conditions assume signal transition times of 1.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0.4V to

2. TestedwiththeloadinFigure1b.Transitionismeasured±500mVfromsteady-statevoltage.Not100%tested.

3. Not 100% tested.