Electronic Components Datasheet Search |
|
IS43DR16320B-3DBI Datasheet(PDF) 8 Page - Integrated Silicon Solution, Inc |
|
IS43DR16320B-3DBI Datasheet(HTML) 8 Page - Integrated Silicon Solution, Inc |
8 / 30 page IS43/46DR86400B, IS43/46DR16320B Integrated Silicon Solution, Inc. – www.issi.com – 8 Rev. I, 8/01/2012 DDR2 Extended Mode Register 2 (EMR[2]) Setting The extended mode register 2 controls refresh related features. The default value of the extended mode register 2 is not defined. Therefore, the extended mode register must be programmed during initialization for proper operation. The extended mode register 2 is written by asserting LOW on CS, RAS, CAS, WE, BA0, and HIGH on BA1, while controlling pins A0-A13. The DDR2 SDRAM should be in all bank precharge state with CKE already HIGH prior to writing into extended mode register 2. The mode register set command cycle time (tMRD) must be satisfied to complete the write operation to the extended mode register 2. Mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in precharge state. Extended Mode Register 2 (EMR[2]) Diagram Address Field Mode Register BA1 1 BA0 0 A13 (1) 0 A7 0 1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 - Full Array 1/2 Array 1/4 Array Reserved 3/4 array 1/2 array 1/4 array Partial Array Self Refresh for 4 Banks BA [1, 0] 00, 01, 10, 11 Reserved 00, 01 00 - 01, 10, 11 10, 11 11 A0 A2 PASR (3) A1 A0 A4 (1) 0 A3 (1) 0 A6 (1) 0 A5 (1) 0 A2 A1 A8 (1) 0 High Temperature Self-Refresh Rate Enable A7 SRFt Disable Enable (2) A10 (1) 0 A9 (1) 0 A12 (1) 0 A11 (1) 0 Notes: 1. A3-A6, and A8-A13 are reserved for future use and must be set to 0 when programming the EMR[2]. 2. Only Industrial and Automotive grade devices support the high temperature Self-Refresh Mode. The controller can set the EMR (2) [A7] bit to enable this self- refresh rate if Tc > 85°C while in self-refresh operation. TOPER may not be violated. 3. If PASR (Partial Array Self Refresh) is enabled, data located in areas of the array beyond the specified address range will be lost if self refresh is entered. Data integrity will be maintained if tREF conditions are met and no Self Refresh command is issued. |
Similar Part No. - IS43DR16320B-3DBI |
|
Similar Description - IS43DR16320B-3DBI |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |