ADP3209

Rev. 2 | Page 9 of 32 | www.onsemi.com

Pin No.

Mnemonic

Description

21

SW

Current Return For High-Side Gate Drive.

22

DRVH

High-Side Gate Drive Output.

23

BST

High-Side Bootstrap Supply. A capacitor from this pin to SW holds the bootstrapped voltage while

the high-side MOSFET is on.

24

VCC

Power Supply Input/Output of the Controller.

25 to 29

VID4 to VID0

Voltage Identification DAC Inputs. A 5-bit word (the VID code) programs the DAC output voltage, the

reference voltage of the voltage error amplifier without a load (see the VID code table, Table 4). In

normal operation mode, the VID DAC output programs the output voltage to a value within the 0 V to

1.25 V range. The input is actively pulled down.

30

EN

Enable Input. Driving this pin low shuts down the chip, disables the driver outputs, and pulls PWRGD low.

31

PWRGD

Power-Good Output. Open-drain output. A low logic state means that the output voltage is outside

of the VID DAC defined range.

32

VARFREQ

Variable Frequency Enable Input. Pulling this pin to ground sets the normal RPM mode of operation.

Pulling this pin to 5 V sets the fixed-frequency PWM mode of operation.