LPC11C14FBD48 datasheet(19/62 Pages) NXP

Part #	LPC11C14FBD48

Description	32-bit ARM Cortex-M0 microcontroller; 16/32 kB flash, 8 kB SRAM; C_CAN

Download	62 Pages

Scroll/Zoom	100%

Manufacturer	NXP [NXP Semiconductors]

Direct Link	http://www.nxp.com

Logo

19 / 62 page

LPC11CX2_CX4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3.1 — 15 May 2013

19 of 62

NXP Semiconductors

LPC11Cx2/Cx4

32-bit ARM Cortex-M0 microcontroller

The I2C-bus is bidirectional for inter-IC control using only two wires: a Serial CLock line

(SCL) and a Serial DAta line (SDA). Each device is recognized by a unique address and

can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the

capability to both receive and send information (such as memory). Transmitters and/or

receivers can operate in either master or slave mode, depending on whether the chip has

to initiate a data transfer or is only addressed. The I2C is a multi-master bus and can be

controlled by more than one bus master connected to it.

7.10.1 Features

• The I2C-interface is a standard I2C-bus compliant interface with open-drain pins. The

I2C-bus interface also supports Fast-mode Plus with bit rates up to 1 Mbit/s.

• Easy to configure as master, slave, or master/slave.

• Programmable clocks allow versatile rate control.

• Bidirectional data transfer between masters and slaves.

• Multi-master bus (no central master).

• Arbitration between simultaneously transmitting masters without corruption of serial

data on the bus.

• Serial clock synchronization allows devices with different bit rates to communicate via

one serial bus.

• Serial clock synchronization can be used as a handshake mechanism to suspend and

resume serial transfer.

• The I2C-bus can be used for test and diagnostic purposes.

• The I2C-bus controller supports multiple address recognition and a bus monitor mode.

7.11 C_CAN controller

Controller Area Network (CAN) is the definition of a high performance communication

protocol for serial data communication. The C_CAN controller is designed to provide a full

implementation of the CAN protocol according to the CAN Specification Version 2.0B. The

C_CAN controller allows to build powerful local networks with low-cost multiplex wiring by

supporting distributed real-time control with a very high level of security.

On-chip C_CAN drivers provide an API for initialization and communication using CAN

and CANopen standards.

7.11.1 Features

• Conforms to protocol version 2.0 parts A and B.

• Supports bit rate of up to 1 Mbit/s.

• Supports 32 Message Objects.

• Each Message Object has its own identifier mask.

• Provides programmable FIFO mode (concatenation of Message Objects).

• Provides maskable interrupts.

• Supports Disabled Automatic Retransmission (DAR) mode for time-triggered CAN

applications.

• Provides programmable loop-back mode for self-test operation.

Similar Part No. - LPC11C14FBD48

Manufacturer	Part #	Datasheet	Description
NXP Semiconductors	LPC11C14FBD48	1Mb / 61P	32-bit ARM Cortex-M0 microcontroller; 16/32 kB flash, 8 kB SRAM C_CAN Rev. 2-3 December 2010
	LPC11C14FBD48-301	290Kb / 2P	NXP 50-MHz, 32-bit Cortex-M0??MCUs January 2011
	LPC11C14FBD48-301	520Kb / 62P	32-bit ARM Cortex-M0 microcontroller; 16/32 kB flash, 8 kB SRAM; C_CAN Rev. 3-27 June 2011
	LPC11C14FBD48/301	310Kb / 49P	32-bit ARM Cortex-M0 microcontroller; 16/32 kB flash, 8 kB SRAM; C_CAN Rev. 00.05-6 May 2010
	LPC11C14FBD48/301	550Kb / 64P	32-bit ARM Cortex-M0 microcontroller; 16/32 kB flash, 8 kB SRAM; C_CAN Rev. 3.2-4 January 2016

More results

Similar Description - LPC11C14FBD48

Manufacturer	Part #	Datasheet	Description
NXP Semiconductors	LPC11CX2	520Kb / 62P	32-bit ARM Cortex-M0 microcontroller; 16/32 kB flash, 8 kB SRAM; C_CAN Rev. 3-27 June 2011
	LPC11C12	310Kb / 49P	32-bit ARM Cortex-M0 microcontroller; 16/32 kB flash, 8 kB SRAM; C_CAN Rev. 00.05-6 May 2010
	LPC11CX2	1Mb / 61P	32-bit ARM Cortex-M0 microcontroller; 16/32 kB flash, 8 kB SRAM C_CAN Rev. 2-3 December 2010
	LPC11CX2	550Kb / 64P	32-bit ARM Cortex-M0 microcontroller; 16/32 kB flash, 8 kB SRAM; C_CAN Rev. 3.2-4 January 2016
	LPC1102_1106	301Kb / 39P	32-bit ARM Cortex-M0 microcontroller; 32 kB flash and 8 kB SRAM Rev. 4-24 June 2011
	LPC1102	683Kb / 43P	32-bit ARM Cortex-M0 microcontroller; 32 kB flash and 8 kB SRAM Rev. 7-26 September 2013
	LPC1102	292Kb / 39P	32-bit ARM Cortex-M0 microcontroller; 32 kB flash and 8 kB SRAM Rev. 3-18 April 2011
	LPC1102	255Kb / 38P	32-bit ARM Cortex-M0 microcontroller; 32 kB flash and 8 kB SRAM Rev. 00.04-23 June 2010
	LPC1111	410Kb / 59P	32-bit ARM Cortex-M0 microcontroller; up to 32 kB flash and 8 kB SRAM Rev. 01-16 April 2010
	LPC1111	621Kb / 64P	32-bit ARM Cortex-M0 microcontroller; up to 32 kB flash and 8 kB SRAM Rev. 5-22 June 2011

More results

LPC11C14FBD48 Datasheet(PDF) 19 Page - NXP Semiconductors

LPC11C14FBD48 Datasheet(HTML) 19 Page - NXP Semiconductors

Similar Part No. - LPC11C14FBD48

Similar Description - LPC11C14FBD48

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62

Datasheet Download

Link URL