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LPC11C14FBD48 Datasheet(PDF) 19 Page - NXP Semiconductors |
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LPC11C14FBD48 Datasheet(HTML) 19 Page - NXP Semiconductors |
19 / 62 page LPC11CX2_CX4 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3.1 — 15 May 2013 19 of 62 NXP Semiconductors LPC11Cx2/Cx4 32-bit ARM Cortex-M0 microcontroller The I2C-bus is bidirectional for inter-IC control using only two wires: a Serial CLock line (SCL) and a Serial DAta line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the capability to both receive and send information (such as memory). Transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. The I2C is a multi-master bus and can be controlled by more than one bus master connected to it. 7.10.1 Features • The I2C-interface is a standard I2C-bus compliant interface with open-drain pins. The I2C-bus interface also supports Fast-mode Plus with bit rates up to 1 Mbit/s. • Easy to configure as master, slave, or master/slave. • Programmable clocks allow versatile rate control. • Bidirectional data transfer between masters and slaves. • Multi-master bus (no central master). • Arbitration between simultaneously transmitting masters without corruption of serial data on the bus. • Serial clock synchronization allows devices with different bit rates to communicate via one serial bus. • Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer. • The I2C-bus can be used for test and diagnostic purposes. • The I2C-bus controller supports multiple address recognition and a bus monitor mode. 7.11 C_CAN controller Controller Area Network (CAN) is the definition of a high performance communication protocol for serial data communication. The C_CAN controller is designed to provide a full implementation of the CAN protocol according to the CAN Specification Version 2.0B. The C_CAN controller allows to build powerful local networks with low-cost multiplex wiring by supporting distributed real-time control with a very high level of security. On-chip C_CAN drivers provide an API for initialization and communication using CAN and CANopen standards. 7.11.1 Features • Conforms to protocol version 2.0 parts A and B. • Supports bit rate of up to 1 Mbit/s. • Supports 32 Message Objects. • Each Message Object has its own identifier mask. • Provides programmable FIFO mode (concatenation of Message Objects). • Provides maskable interrupts. • Supports Disabled Automatic Retransmission (DAR) mode for time-triggered CAN applications. • Provides programmable loop-back mode for self-test operation. |
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