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AD8403ARUZ10 Datasheet(PDF) 10 Page - Analog Devices |
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AD8403ARUZ10 Datasheet(HTML) 10 Page - Analog Devices |
10 / 32 page AD8400/AD8402/AD8403 Rev. E | Page 10 of 32 ELECTRICAL CHARACTERISTICS—ALL VERSIONS VDD = 3 V ± 10% or 5 V ± 10%, VA = VDD, VB = 0 V, −40°C ≤ TA ≤ +125°C, unless otherwise noted. Table 4. Parameter Symbol Conditions Min Typ1 Max Unit SWITCHING CHARACTERISTICS2, 3 Input Clock Pulse Width tCH, tCL Clock level high or low 10 ns Data Setup Time tDS 5 ns Data Hold Time tDH 5 ns CLK to SDO Propagation Delay4 tPD RL = 1 kΩ to 5 V, CL ≤ 20 pF 1 25 ns CS Setup Time tCSS 10 ns CS High Pulse Width tCSW 10 ns Reset Pulse Width tRS 50 ns CLK Fall to CS Rise Hold Time tCSH 0 ns CS Rise to Clock Rise Setup tCS1 10 ns 1 Typicals represent average readings at 25°C and VDD = 5 V. 2 Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remaining resistor terminals are left open circuit. 3 See the timing diagram in Figure 3 for location of measured values. All input control voltages are specified with tR = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. Switching characteristics are measured using VDD = 3 V or 5 V. To avoid false clocking, a minimum input logic slew rate of 1 V/μs should be maintained. 4 Propagation delay depends on the value of VDD, RL, and CL (see the Applications section). TIMING DIAGRAMS DAC REGISTER LOAD A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 0 1 0 VDD 0V SDI CLK VOUT CS Figure 3. Timing Diagram ±1% ERROR BAND ±1% tCSH tCSS tDH Ax OR Dx Ax OR Dx tPD_MIN tPD_MAX A'x OR D'x A'x OR D'x 1 0 1 0 1 0 VDD 0V SDI (DATA IN) CLK CS VOUT 1 0 SDO (DATA OUT) tDS tCH tCS1 tCL tS tCSW Figure 4. Detailed Timing Diagram ±1% ±1% ERROR BAND 1 0 VDD VDD/2 VOUT tRS tS RS Figure 5. Reset Timing Diagram |
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