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S25FL032P0XNFI010 Datasheet(PDF) 11 Page - SPANSION |
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S25FL032P0XNFI010 Datasheet(HTML) 11 Page - SPANSION |
11 / 69 page January 29, 2013 S25FL032P_00_09 S25FL032P 11 Data Sheet Figure 2.6 6x8 mm 24-ball BGA Package, 6x4 pin Configuration 3. Input/Output Descriptions SCK NC NC GND VCC B2 B3 B4 CS# NC W#/ACC/IO2 C1 C2 C3 C4 SO/IO1 SI/IO0 HOLD#/IO3 D1 D2 D3 D4 NC NC NC E1 E2 E3 NC E4 NC NC NC A2 A3 A4 B1 NC NC NC NC F1 F2 F3 NC F4 NC A1 Signal I/O Description SO/IO1 I/O Serial Data Output: Transfers data serially out of the device on the falling edge of SCK. Functions as an input pin in Dual and Quad I/O, and Quad Page Program modes. SI/IO0 I/O Serial Data Input: Transfers data serially into the device. Device latches commands, addresses, and program data on SI on the rising edge of SCK. Functions as an output pin in Dual and Quad I/O mode. SCK Input Serial Clock: Provides serial interface timing. Latches commands, addresses, and data on SI on rising edge of SCK. Triggers output on SO after the falling edge of SCK. CS# Input Chip Select: Places device in active power mode when driven low. Deselects device and places SO at high impedance when high. After power-up, device requires a falling edge on CS# before any command is written. Device is in standby mode when a program, erase, or Write Status Register operation is not in progress. HOLD#/IO3 I/O Hold: Pauses any serial communication with the device without deselecting it. When driven low, SO is at high impedance, and all input at SI and SCK are ignored. Requires that CS# also be driven low. Functions as an output pin in Quad I/O mode. W#/ACC/IO2 I/O Write Protect: Protects the memory area specified by Status Register bits BP2:BP0. When driven low, prevents any program or erase command from altering the data in the protected memory area. Functions as an output pin in Quad I/O mode. VCC Input Supply Voltage GND Input Ground |
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