S25FL128SDPMFIG11 datasheet(38/153 Pages) SPANSION

Part #	S25FL128SDPMFIG11

Description	MirrorBit Flash Non-Volatile Memory CMOS 3.0 Volt Core with Versatile I/O Serial Peripheral Interface with Multi-I/O

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S25FL128S and S25FL256S

S25FL128S_256S_00_05 July 12, 2012

Da ta

Sh e e t

6.2.1

Capacitance Characteristics

Note:

1. For more information on capacitance, please consult the IBIS models.

6.3

Reset

6.3.1

Power-On (Cold) Reset

The device executes a Power-On Reset (POR) process until a time delay of tPU has elapsed after the

moment that VCC rises above the minimum VCC threshold. See Figure 5.3 on page 35, Table 5.2 on page 35,

and Table 6.3 on page 39. The device must not be selected (CS# to go high with VIO) during power-up (tPU),

i.e. no commands may be sent to the device until the end of tPU. RESET# is ignored during POR. If RESET#

is low during POR and remains low through and beyond the end of tPU, CS# must remain high until tRH after

RESET# returns high. RESET# must return high for greater than tRS before returning low to initiate a

hardware reset.

Figure 6.4 Reset Low at the End of POR

Figure 6.5 Reset High at the End of POR

Figure 6.6 POR followed by Hardware Reset

Table 6.2 Capacitance

Parameter

Test Conditions

Min

Max

Unit

CIN

Input Capacitance (applies to SCK, CS#, RESET#)

1 MHz

8

pF

COUT

Output Capacitance (applies to All I/O)

1 MHz

8

pF

VCC

VIO

RESET#

CS#

If RESET# is low at tPU end

CS# must be high at tPU end

tPU

tRH

VCC

VIO

RESET#

CS#

If RESET# is high at tPU end

CS# may stay high or go low at tPU end

tPU

VCC

VIO

RESET#

CS#

tRS

tPU

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S25FL128SDPMFIG11 Datasheet(PDF) 38 Page - SPANSION

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