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LNK304DGTL Datasheet(PDF) 3 Page - Power Integrations, Inc. |
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LNK304DGTL Datasheet(HTML) 3 Page - Power Integrations, Inc. |
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3 / 20 page  2-3 LNK302/304-306 3 Rev. I 11/08 Pin Functional Description DRAIN (D) Pin: Power MOSFET drain connection. Provides internal operating current for both start-up and steady-state operation. BYPASS (BP) Pin: Connection point for a 0.1 μF external bypass capacitor for the internally generated 5.8 V supply. FEEDBACK (FB) Pin: During normal operation, switching of the power MOSFET is controlled by this pin. MOSFET switching is terminated when a current greater than 49 μA is delivered into this pin. SOURCE (S) Pin: This pin is the power MOSFET source connection. It is also the ground reference for the BYPASS and FEEDBACK pins. LinkSwitch-TN Functional Description LinkSwitch-TN combines a high voltage power MOSFETswitch with a power supply controller in one device. Unlike conventional PWM (pulse width modulator) controllers, LinkSwitch-TN uses a simple ON/OFF control to regulate the output voltage. The LinkSwitch-TN controller consists of an oscillator, feedback (sense and logic) circuit, 5.8 V regulator, BYPASS pin under- voltage circuit, over-temperature protection, frequency jittering, current limit circuit, leading edge blanking and a 700 V power MOSFET. The LinkSwitch-TN incorporates additional circuitry for auto-restart. Oscillator The typical oscillator frequency is internally set to an average of 66 kHz. Two signals are generated from the oscillator: the maximum duty cycle signal (DC MAX) and the clock signal that indicates the beginning of each cycle. The LinkSwitch-TN oscillator incorporates circuitry that introduces a small amount of frequency jitter, typically 4 kHz peak-to-peak, to minimize EMI emission. The modulation rate of the frequency jitter is set to 1 kHz to optimize EMI reduction for both average and quasi-peak emissions. The frequency jitter should be measured with the oscilloscope triggered at the falling edge of the DRAIN waveform. The waveform in Figure 4 illustrates the frequency jitter of the LinkSwitch-TN. Feedback Input Circuit The feedback input circuit at the FB pin consists of a low impedance source follower output set at 1.65V.When the current delivered into this pin exceeds 49 μA, a low logic level (disable) is generated at the output of the feedback circuit. This output is sampled at the beginning of each cycle on the rising edge of the clock signal. If high, the power MOSFET is turned on for that cycle (enabled), otherwise the power MOSFET remains off (disabled). Since the sampling is done only at the beginning of each cycle, subsequent changes in the FB pin voltage or current during the remainder of the cycle are ignored. 5.8 V Regulator and 6.3 V Shunt Voltage Clamp The 5.8 V regulator charges the bypass capacitor connected to the BYPASS pin to 5.8 V by drawing a current from the voltage on the DRAIN, whenever the MOSFET is off. The BYPASS pin is the internal supply voltage node for the LinkSwitch-TN. When the MOSFET is on, the LinkSwitch-TN runs off of the energy stored in the bypass capacitor. Extremely low power consumption of the internal circuitry allows the LinkSwitch-TN to operate continuously from the current drawn from the DRAIN pin. A bypass capacitor value of 0.1 μF is sufficient for both high frequency decoupling and energy storage. In addition, there is a 6.3 V shunt regulator clamping the BYPASS pin at 6.3 V when current is provided to the BYPASS pin through an external resistor. This facilitates powering of LinkSwitch-TN externally through a bias winding to decrease the no-load consumption to about 50 mW. BYPASS Pin Under-Voltage The BYPASS pin under-voltage circuitry disables the power MOSFET when the BYPASS pin voltage drops below 4.85 V. Once the BYPASS pin voltage drops below 4.85 V, it must rise back to 5.8 V to enable (turn-on) the power MOSFET. Over-Temperature Protection The thermal shutdown circuitry senses the die temperature. The threshold is set at 142 °C typical with a 75 °C hysteresis. When the die temperature rises above this threshold (142 °C)the power MOSFET is disabled and remains disabled until the die temperature falls by 75 °C, at which point it is re-enabled. Current Limit The current limit circuit senses the current in the power MOSFET. When this current exceeds the internal threshold (I LIMIT), the PI-3491-120706 3a 3b FB D S BP S S S P Package (DIP-8B) G Package (SMD-8B) D Package (SO-8C) 8 5 7 1 4 2 3 D S FB S S BP 8 5 7 1 4 2 S 6 Figure 3. Pin Configuration. |
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