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EPF6024AQC240-3 Datasheet(PDF) 9 Page - Altera Corporation |
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EPF6024AQC240-3 Datasheet(HTML) 9 Page - Altera Corporation |
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9 / 52 page  Altera Corporation 9 FLEX 6000 Programmable Logic Device Family Data Sheet Figure 4. Logic Element The programmable flipflop in the LE can be configured for D, T, JK, or SR operation. The clock and clear control signals on the flipflop can be driven by global signals, general-purpose I/O pins, or any internal logic. For combinatorial functions, the flipflop is bypassed and the output of the LUT drives the outputs of the LE. The LE output can drive both the local interconnect and the FastTrack Interconnect. The FLEX 6000 architecture provides two types of dedicated high-speed data paths that connect adjacent LEs without using local interconnect paths: carry chains and cascade chains. A carry chain supports high-speed arithmetic functions such as counters and adders, while a cascade chain implements wide-input functions such as equivalent comparators with minimum delay. Carry and cascade chains connect LEs 2 through 10 in an LAB and all LABs in the same half of the row. Because extensive use of carry and cascade chains can reduce routing flexibility, these chains should be limited to speed-critical portions of a design. Chip-Wide Reset Carry-In Clock Select Carry-Out Look-Up T able (LUT) Clear/ Preset Logic Carry Chain Cascade Chain Cascade-In Cascade-Out LE-Out Programmable Register PRN CLRN DQ Register Bypass data1 data2 data3 data4 labctrl1 labctrl2 labctrl3 labctrl4 |
Similar Part No. - EPF6024AQC240-3 |
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Similar Description - EPF6024AQC240-3 |
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