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AFCT-5179AZ Datasheet(PDF) 4 Page - AVAGO TECHNOLOGIES LIMITED

Part # AFCT-5179AZ
Description  SC Duplex Single Mode Transceiver Multisourced 1 x 9 pin configuration
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Manufacturer  AVAGO [AVAGO TECHNOLOGIES LIMITED]
Direct Link  http://www.avagotech.com
Logo AVAGO - AVAGO TECHNOLOGIES LIMITED

AFCT-5179AZ Datasheet(HTML) 4 Page - AVAGO TECHNOLOGIES LIMITED

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4
Transmitter Section
Design
The transmitter section, Figure 3, uses a Multiple Quantum
Well laser as its optical source. The package of this laser is
designed to allow repeatable coupling into single mode
fiber. In addition, this package has been designed to be
compliant with IEC 825 Class 1 and CDRH Class I eye safety
requirements. The optical output is controlled by a custom
IC which detects the laser output via the monitor photo-
diode. This IC provides both dc and ac current drive to
the laser to ensure correct modulation, eye diagram and
extinction ratio over temperature, supply voltage and life.
PCB mounting
The AFCT-5179xZ has two solderable mounting studs,
Figures 5 and 6. These studs are not electrically connected.
The transceiver is designed for common production
processes. It may be wave soldered and aqueous washed
providing the process plug is in place.
Each process plug can only be used once during process-
ing, although with subsequent use, it can be used as a
dust cover.
Figure 4. Recommended Circuit Schematic
DATA
DATA
PECL
INPUT
LASER
MODULATOR
LASER
LASER BIAS
DRIVER
LASER BIAS
CONTROL
PHOTODIODE
(rear facet monitor)
Figure 3. Simplified Transmitter Schematic
NO INTERNAL
CONNECTION
NO INTERNAL
CONNECTION
TOP VIEW
V
EER
1
RD
2
SD
4
V
CCR
5
V
CCT
6
TD
8
V
EET
9
NOTES:
THE SPLIT-LOAD TERMINATIONS FOR ECL SIGNALS NEED TO BE LOCATED AT
THE INPUT OF DEVICES RECEIVING THOSE ECL SIGNALS. RECOMMEND 4-LAYER
PRINTED CIRCUIT BOARD WITH 50
Ω MICROSTRIP SIGNAL PATHS BE USED.
R1 = R4 = R6 = R8 = R10 = 130
R2 = R3 = R5 = R7 = R9 = 82
C1 = C2 = 10 µF (see Figure 2)
C3 = C4 = C7 = C8 = 100 nF
C5 = C6 = 0.1 µF
L1 = L2 = 3.3 µH COIL OR FERRITE INDUCTOR.
TERMINATE
AT THE
DEVICE
INPUTS
VccFILTER
AT VccPINS
TRANSCEIVER
V
CC
C8
C1
L1 L2
TD
RD
3
TD
7
R8
RD
RD
V
CC
R5
R7
R6
C6
SD
R10
C7
C2
C3
C4
R4
V
CC
R2
R3
R1
TERMINATION
AT
TRANSCEIVER
INPUTS
TD
C5
R9


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