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AFCT-5179AZ Datasheet(PDF) 3 Page - AVAGO TECHNOLOGIES LIMITED

Part # AFCT-5179AZ
Description  SC Duplex Single Mode Transceiver Multisourced 1 x 9 pin configuration
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Manufacturer  AVAGO [AVAGO TECHNOLOGIES LIMITED]
Direct Link  http://www.avagotech.com
Logo AVAGO - AVAGO TECHNOLOGIES LIMITED

AFCT-5179AZ Datasheet(HTML) 3 Page - AVAGO TECHNOLOGIES LIMITED

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Functional Description
Receiver Section
Design
The receiver section contains an InGaAs/InP photo
detector and a preamplifier within the receptacle, coupled
to a postamplifier/decision circuit on a separate circuit
board.
The postamplifier is ac coupled to the preamplifier as illus-
trated in Figure 1. The coupling capacitor is large enough
to pass the EFM test pattern at 125 MBd without signifi-
cant distortion or performance penalty.
Figure 1 also shows a filter network which limits the band-
width of the preamp output signal. The filter is designed
to bandlimit the preamp output noise and thus improve
the receiver sensitivity.
These components will also reduce the sensitivity of the
receiver as the signal bit rate is increased above 155 MBd.
Noise Immunity
The receiver includes internal circuit components to filter
power supply noise. Under some conditions of EMI and
power supply noise, external power supply filtering may
be necessary. If receiver sensitivity is found to be degraded
by power supply noise, the filter network illustrated in
Figure 2 may be used to improve performance. The values
of the filter components are general recommendations
and may be changed to suit a particular system environ-
ment. Shielded inductors are recommended.
Figure 1. Receiver Block Diagram
Terminating the Outputs
The PECL Data outputs of the receiver may be terminated
with the standard Thevenin-equivalent 50 ohm to VCC
2 V termination.
Other standard PECL terminating techniques may be
used.
The two outputs of the receiver should be terminated
with identical load circuits to avoid unnecessarily large
ac current in VCC. If the outputs are loaded identically the
ac current is largely nulled. The Signal Detect output of
the receiver is PECL logic and must be loaded if it is to be
used. The Signal Detect circuit is much slower than the
data path, so the ac noise generated by an asymmetrical
load is negligible. Power consumption may be reduced by
using a higher than normal load impedance for the Signal
Detect output. Transmission line effects are not generally
a problem as the switching rate is slow.
The Signal Detect Circuit
The Signal Detect circuit works by sensing the peak
level of the received signal and comparing this level to a
reference.
Figure 2. Filter Network for Noise Filtering
RECEIVER
RECEPTACLE
TRANS-
IMPEDANCE
PRE-
AMPLIFIER
FILTER
GND
LIMITING
AMPLIFIER
PECL
OUTPUT
BUFFER
PECL
OUTPUT
BUFFER
DATA OUT
SIGNAL
DETECT
CIRCUIT
SD
DATA OUT
VCC
100 nF
3.3 µH
100 nF
10 µF
FILTERED VCCto DATA LINK
+


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