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HFBR-772BEPWZ Datasheet(PDF) 11 Page - AVAGO TECHNOLOGIES LIMITED |
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HFBR-772BEPWZ Datasheet(HTML) 11 Page - AVAGO TECHNOLOGIES LIMITED |
11 / 25 page 11 Table 1. Transmitter Module Pad Description Symbol Functional Description VEE Transmitter Signal Common. All voltages are referenced to this potential unless otherwise indicated. Directly connect these pads to transmitter signal ground plane. VCCT Transmitter Power Supply. Use recommended power supply filter circuit in Figure 6. DIN0+ through DIN11+ Transmitter Data In+ for channels 0 through 11, respectively. Differential termination and self bias are included, see Figure 11. DIN0– through DIN11– Transmitter Data In- for channels 0 through 11, respectively. Differential termination and self bias are included; see Figure 11. TX_EN TX Enable. Active high. Internal pull-up High = VCSEL array is enabled if TX_DIS is inactive (Low).Low = VCSEL array is off. TX_EN must be taken to a logic low state level (VOL) for 1 ms or longer. TX_DIS TX Disable. Active high. Internal pull-down Low = VCSEL array is enabled if TX_EN is active (High).High = VCSEL array is off. TX_DIS must be taken to a logic High state level (VOH) for 1 ms or longer. RESET- Transmitter RESET- input. Active low. Internal pull-up. Low = Resets logic function clears FAULT- signal, VCSEL array is off. high = Normal operation. See Figure 14. FAULT- Transmitter FAULT- output. Active low. Low (logic “0”) results from a VCSEL over-current con- dition, out of temperature range, or EEPROM calibration data corruption condition detected for any VCSEL. An asserted (logic “0”) FAULT- disables the VCSEL array and is cleared by RESET- or power cycling VCCT FAULT- is a single ended LVTTL compatible output. DNC Do not connect to any electrical potential. Table 2. Receiver Module Pad Description Symbol Functional Description VEE Receiver Signal Common. All voltages are referenced to this potential unless otherwise indicated.Directly connect these pads to receiver signal ground plane. VCCR Receiver Power Supply. Use recommended power supply filter circuit in Figure 5. VPP Not required for Avago product. Pads not internally connected.(Voltage for MSA compatibil- ity in order to ac-couple receiver data outputs). DOUT0+ through DOUT11+ Receiver Data Out+ for channels 0 through 11, respectively. Terminate these high-speed differential CML outputs with standard CML techniques at the inputs of the receiving device. Individual data outputs will be squelched for insufficient input signal level. DOUT0– through DOUT11– Receiver Data Out- for channel 0 through 11, respectively. Terminate these high-speed dif- ferential CML outputs with standard CML techniques at the inputs of the receiving device. Individual data outputs will be squelched for insufficient input signal level. SD Signal Detect. Normal optical input levels to all channels results in a logic “1” output, VOH, asserted. Low input optical levels to any channel results in a fault condition indicated by a logic “0” output, VOL, de-asserted. SD is a single-ended LVTTL compatible output. RX_EN Receiver output enable. Active high (logic “1”), internal pull-up. Low (logic “0”) = receiver outputs disabled, all outputs are high (logic “1”). SQ_EN Squelch enable input. Active high (logic “1”), internal pull-up. Low (logic “0”) = squelch dis- abled. When SQ_EN is high and SD is low, corresponding outputs are squelched. EN_SD Enable Signal Detect. Active high (logic “1”), internal pull-up. Low (logic “0”) = Signal detect output forced active high. DNC Do not connect to any electrical potential. |
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